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/Zephyr-latest/dts/arm/silabs/
Defm32gg11b820f2048gl192.dtsi13 reg = <0x20000000 DT_SIZE_K(256)>;
21 flash0: flash@0 {
22 reg = <0 DT_SIZE_K(2048)>;
28 reg = <0x40024000 0xC14>;
29 interrupts = <59 0>;
/Zephyr-latest/dts/bindings/can/
Dnxp,flexcan.yaml11 reg = <0x40024000 0x1000>;
12 interrupts = <78 0>, <79 0>, <80 0>, <81 0>;
13 interrupt-names = "warning", "error", "wake-up", "mb-0-15";
16 pinctrl-0 = <&pinmux_flexcan0>;
/Zephyr-latest/dts/arm/ti/
Dlm3s6965.dtsi8 #size-cells = <0>;
10 cpu@0 {
13 reg = <0>;
19 reg = <0x20000000 (64*1024)>;
25 #clock-cells = <0>;
32 reg = <0x400fd000 0x1000>;
36 flash0: flash@0 {
38 reg = <0x00000000 (256*1024)>;
44 reg = <0x4000c000 0x4c>;
52 reg = <0x4000d000 0x4c>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f446.dtsi24 #size-cells = <0>;
25 reg = <0x40013000 0x400>;
28 dmas = <&dma2 3 3 0x400 0x3
29 &dma2 2 3 0x400 0x3>;
36 reg = <0x40004800 0x400>;
39 interrupts = <39 0>;
45 reg = <0x40004c00 0x400>;
48 interrupts = <52 0>;
54 reg = <0x40005000 0x400>;
57 interrupts = <53 0>;
[all …]
Dstm32f405.dtsi19 reg = <0x40020000 0x2400>;
25 reg = <0x40021400 0x400>;
33 reg = <0x40021800 0x400>;
41 reg = <0x40022000 0x400>;
48 reg = <0x40004800 0x400>;
51 interrupts = <39 0>;
57 reg = <0x40004c00 0x400>;
60 interrupts = <52 0>;
66 reg = <0x40005000 0x400>;
69 interrupts = <53 0>;
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsam4l.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
31 reg = <0xe000ed90 0x40>;
48 reg = <0x21000000 DT_SIZE_K(4)>;
55 reg = <0x400e0000 0x740>;
56 interrupts = <22 0>;
63 reg = <0x400a0000 0x400>;
64 interrupts = <0 0>;
68 flash0: flash@0 {
[all …]
Dsam4s.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0>;
37 reg = <0xe000ed90 0x40>;
45 reg = <0x400e0400 0x200>;
46 interrupts = <5 0>;
53 reg = <0x400e1410 0x20>;
64 reg = <0x400e0a00 0x200>;
65 interrupts = <6 0>;
81 reg = <0x400e1450 0xc>;
[all …]
Dsame70.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0>;
41 reg = <0xe000ed90 0x40>;
53 reg = <0x400e0600 0x200>;
54 interrupts = <5 0>;
61 reg = <0x400e1810 0x20>;
68 reg = <0x400e0c00 0x200>;
69 interrupts = <6 0>;
85 reg = <0x400e1850 0xc>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4xxx.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
20 reg = <0>;
26 reg = <0x58001000 0x1400>;
38 #clock-cells = <0>;
44 reg = <0x40044000 0xff>, <0x50004800 0xff>;
54 reg = <0x48028000 0x1000>;
62 reg = <0x48028000 0x100>;
70 reg = <0x48028100 0x100>;
78 reg = <0x48028200 0x100>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_s32k1xx.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
22 reg = <0>;
37 reg = <0x4000d000 0x1000>;
43 reg = <0x40020000 0x1000>;
44 interrupts = <18 0>, <19 0>, <21 0>;
53 reg = <0x40024000 0x1000>;
61 reg = <0x40025000 0x1000>;
68 reg = <0x4002b000 0x1000>;
75 reg = <0x4002c000 0x1000>;
[all …]
Dnxp_k6x.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0>;
34 * across the 0x2000_0000 boundary are not supported in the Arm
43 reg = <0x1fff0000 DT_SIZE_K(64)>;
49 reg = <0x20000000 DT_SIZE_K(192)>;
85 reg = <0x4000d000 0x824>;
92 reg = <0x40064000 0xd>;
98 reg = <0x40065000 0x4>;
105 reg = <0x4003d000 0x1000>;
[all …]
Dnxp_ke1xf.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0>;
43 substate-id = <0>;
106 reg = <0x40008000 0x1000>, <0x40021000 0x1000>;
107 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
108 <4 0>, <5 0>, <6 0>, <7 0>,
109 <8 0>, <9 0>, <10 0>, <11 0>,
110 <12 0>, <13 0>, <14 0>, <15 0>,
111 <16 0>;
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
68 reg = <0x10000000 0x10000>;
75 reg = <0x10010000 0x2B0000>;
83 reg = <0x00018000 0x1e8000>;
91 reg = <0x00018000 0x1e8000>;
97 reg = <0x40021000 0x400>;
[all …]
Dambiq_apollo4p_blue.dtsi14 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0>;
40 reg = <0xe0000000 0x1000>;
49 reg = <0x10000000 0x10000>;
56 reg = <0x10010000 0x2B0000>;
64 reg = <0x00018000 0x1e8000>;
72 reg = <0x00018000 0x1e8000>;
78 reg = <0x40021000 0x400>;
[all …]
Dambiq_apollo3_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0x50000>;
79 flash: flash-controller@0 {
81 reg = <0x00000000 0x100000>;
87 flash0: flash@0 {
[all …]
Dambiq_apollo3p_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0xB0000>;
78 reg = <0x52000000 0x2000000>;
84 reg = <0x54000000 0x2000000>;
90 reg = <0x56000000 0x2000000>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/
Dm2l31x.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
39 #clock-cells = <0>;
45 reg = <0x40000200 0x100>;
46 #clock-cells = <0>;
62 reg = <0x40000000 0x20>;
68 reg = <0x4000c000 0x1000>;
72 flash0: flash@0 {
81 reg = <0x40070000 0x1000>;
[all …]
Dm46x.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
38 reg = <0x20000000 DT_SIZE_K(512)>;
44 #clock-cells = <0>;
50 reg = <0x40000200 0x100>;
51 #clock-cells = <0>;
68 reg = <0x40000000 0x20>;
75 reg = <0x4000c000 0x110>;
79 flash0: flash@0 {
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0>;
52 #clock-cells = <0>;
53 #address-cells = <0>;
61 #clock-cells = <0>;
69 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
93 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/nordic/
Dnrf52832.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52840.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52833.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
57 #clock-cells = <0>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
80 reg = <0x40023c00 0x400>;
81 interrupts = <4 0>;
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
43 reg = <0xe000ed90 0x40>;
50 reg = <0x90000000 DT_SIZE_M(256)>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
73 driving-capability = <0>;
78 #clock-cells = <0>;
[all …]