Lines Matching +full:0 +full:x40024000
15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
68 reg = <0x10000000 0x10000>;
75 reg = <0x10010000 0x2B0000>;
83 reg = <0x00018000 0x1e8000>;
91 reg = <0x00018000 0x1e8000>;
97 reg = <0x40021000 0x400>;
103 reg = <0x40008800 0x80>;
104 interrupts = <32 0>;
110 reg = <0x40008200 0x20>;
111 interrupts = <67 0>;
119 reg = <0x4001c000 0x1000>;
120 interrupts = <15 0>;
124 ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
128 reg = <0x4001d000 0x1000>;
129 interrupts = <16 0>;
133 ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
138 reg = <0x4001e000 0x1000>;
139 interrupts = <17 0>;
143 ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
148 reg = <0x4001f000 0x1000>;
149 interrupts = <18 0>;
153 ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
157 reg = <0x40050000 0x1000>;
159 #size-cells = <0>;
160 interrupts = <6 0>;
162 ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
166 reg = <0x40050000 0x1000>;
168 #size-cells = <0>;
169 interrupts = <6 0>;
171 ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
175 reg = <0x40051000 0x1000>;
177 #size-cells = <0>;
178 interrupts = <7 0>;
180 ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
184 reg = <0x40051000 0x1000>;
186 #size-cells = <0>;
187 interrupts = <7 0>;
189 ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
193 reg = <0x40052000 0x1000>;
195 #size-cells = <0>;
196 interrupts = <8 0>;
198 ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
202 reg = <0x40052000 0x1000>;
204 #size-cells = <0>;
205 interrupts = <8 0>;
207 ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
211 reg = <0x40053000 0x1000>;
213 #size-cells = <0>;
214 interrupts = <9 0>;
216 ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
220 reg = <0x40053000 0x1000>;
222 #size-cells = <0>;
223 interrupts = <9 0>;
225 ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
229 reg = <0x40054000 0x1000>;
231 #size-cells = <0>;
232 interrupts = <10 0>;
234 ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
238 reg = <0x40054000 0x1000>;
240 #size-cells = <0>;
241 interrupts = <10 0>;
243 ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
247 reg = <0x40055000 0x1000>;
249 #size-cells = <0>;
250 interrupts = <11 0>;
252 ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
256 reg = <0x40055000 0x1000>;
258 #size-cells = <0>;
259 interrupts = <11 0>;
261 ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
265 reg = <0x40056000 0x1000>;
267 #size-cells = <0>;
268 interrupts = <12 0>;
270 ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
274 reg = <0x40056000 0x1000>;
276 #size-cells = <0>;
277 interrupts = <12 0>;
279 ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
283 reg = <0x40057000 0x1000>;
285 #size-cells = <0>;
286 interrupts = <13 0>;
288 ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
292 reg = <0x40057000 0x1000>;
294 #size-cells = <0>;
295 interrupts = <13 0>;
297 ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
301 reg = <0x40038000 0x400>;
302 interrupts = <19 0>;
308 ambiq,pwrcfg = <&pwrcfg 0x4 0x2000>;
313 reg = <0x40060000 0x400>;
314 interrupts = <20 0>;
316 #size-cells = <0>;
318 ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
323 reg = <0x40061000 0x400>;
324 interrupts = <21 0>;
326 #size-cells = <0>;
328 ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
333 reg = <0x40062000 0x400>;
334 interrupts = <22 0>;
336 #size-cells = <0>;
338 ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
343 reg = <0x40004800 0x210>;
344 interrupts = <2 0>;
351 reg = <0x400B0000 0x4100>;
352 interrupts = <27 0>;
356 ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
361 reg = <0x40010000 0x800>;
363 #size-cells = <0>;
367 gpio-map-mask = <0xffffffe0 0xffffffc0>;
368 gpio-map-pass-thru = <0x1f 0x3f>;
370 0x00 0x0 &gpio0_31 0x0 0x0
371 0x20 0x0 &gpio32_63 0x0 0x0
372 0x40 0x0 &gpio64_95 0x0 0x0
373 0x60 0x0 &gpio96_127 0x0 0x0
375 reg = <0x40010000>;
378 #size-cells = <0>;
381 gpio0_31: gpio0_31@0 {
385 reg = <0>;
386 interrupts = <56 0>;
394 reg = <0x80>;
395 interrupts = <57 0>;
403 reg = <0x100>;
404 interrupts = <58 0>;
412 reg = <0x180>;
413 interrupts = <59 0>;
421 reg = <0x40024000 0x400>;
422 interrupts = <1 0>;