1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/adc/adc.h>
7#include <zephyr/dt-bindings/i2c/i2c.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	clocks {
12		uartclk: apb-pclk {
13			compatible = "fixed-clock";
14			clock-frequency = <DT_FREQ_M(24)>;
15			#clock-cells = <0>;
16		};
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			cpu-power-states = <&idle &suspend_to_ram>;
27			#address-cells = <1>;
28			#size-cells = <1>;
29
30			itm: itm@e0000000 {
31				compatible = "arm,armv7m-itm";
32				reg = <0xe0000000 0x1000>;
33				swo-ref-frequency = <DT_FREQ_M(48)>;
34			};
35		};
36		power-states {
37			idle: idle {
38				compatible = "zephyr,power-state";
39				power-state-name = "suspend-to-idle";
40				/*
41				 * As Apollo4 datasheet, run_to_sleep and sleep_to_run
42				 * transition time are both lower than 1us, but
43				 * considering the software overhead we set a
44				 * bigger value.
45				 */
46				min-residency-us = <100>;
47				exit-latency-us = <5>;
48			};
49
50			suspend_to_ram: suspend_to_ram {
51				compatible = "zephyr,power-state";
52				power-state-name = "suspend-to-ram";
53				/*
54				 * As Apollo4 datasheet, run_to_deepsleep transition
55				 * time is lower than 1us and deepsleep_to_run
56				 * transition time is about 25us, but considering
57				 * the software overhead, we set a bigger value.
58				 */
59				min-residency-us = <2000>;
60				exit-latency-us = <125>;
61			};
62		};
63	};
64
65	/* TCM */
66	tcm: tcm@10000000 {
67		compatible = "zephyr,memory-region";
68		reg = <0x10000000 0x10000>;
69		zephyr,memory-region = "ITCM";
70	};
71
72	/* SRAM */
73	sram0: memory@10010000 {
74		compatible = "mmio-sram";
75		reg = <0x10010000 0x2B0000>;
76	};
77
78	soc {
79		compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
80
81		flash: flash-controller@18000 {
82			compatible = "ambiq,flash-controller";
83			reg = <0x00018000 0x1e8000>;
84
85			#address-cells = <1>;
86			#size-cells = <1>;
87
88			/* Flash region */
89			flash0: flash@18000 {
90				compatible = "soc-nv-flash";
91				reg = <0x00018000 0x1e8000>;
92			};
93		};
94
95		pwrcfg: pwrcfg@40021000 {
96			compatible = "ambiq,pwrctrl";
97			reg = <0x40021000 0x400>;
98			#pwrcfg-cells = <2>;
99		};
100
101		stimer0: stimer@40008800 {
102			compatible = "ambiq,stimer";
103			reg = <0x40008800 0x80>;
104			interrupts = <32 0>;
105			status = "okay";
106		};
107
108		counter0: counter@40008200 {
109			compatible = "ambiq,counter";
110			reg = <0x40008200 0x20>;
111			interrupts = <67 0>;
112			clock-frequency = <DT_FREQ_M(6)>;
113			clk-source = <1>;
114			status = "disabled";
115		};
116
117		uart0: uart@4001c000 {
118			compatible = "ambiq,uart", "arm,pl011";
119			reg = <0x4001c000 0x1000>;
120			interrupts = <15 0>;
121			interrupt-names = "UART0";
122			status = "disabled";
123			clocks = <&uartclk>;
124			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
125		};
126		uart1: uart@4001d000 {
127			compatible = "ambiq,uart", "arm,pl011";
128			reg = <0x4001d000 0x1000>;
129			interrupts = <16 0>;
130			interrupt-names = "UART1";
131			status = "disabled";
132			clocks = <&uartclk>;
133			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
134		};
135
136		uart2: uart@4001e000 {
137			compatible = "ambiq,uart", "arm,pl011";
138			reg = <0x4001e000 0x1000>;
139			interrupts = <17 0>;
140			interrupt-names = "UART2";
141			status = "disabled";
142			clocks = <&uartclk>;
143			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
144		};
145
146		uart3: uart@4001f000 {
147			compatible = "ambiq,uart", "arm,pl011";
148			reg = <0x4001f000 0x1000>;
149			interrupts = <18 0>;
150			interrupt-names = "UART3";
151			status = "disabled";
152			clocks = <&uartclk>;
153			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
154		};
155
156		iom0_spi: spi@40050000 {
157			reg = <0x40050000 0x1000>;
158			#address-cells = <1>;
159			#size-cells = <0>;
160			interrupts = <6 0>;
161			status = "disabled";
162			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
163		};
164
165		iom0_i2c: i2c@40050000 {
166			reg = <0x40050000 0x1000>;
167			#address-cells = <1>;
168			#size-cells = <0>;
169			interrupts = <6 0>;
170			status = "disabled";
171			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
172		};
173
174		iom1_spi: spi@40051000 {
175			reg = <0x40051000 0x1000>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			interrupts = <7 0>;
179			status = "disabled";
180			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
181		};
182
183		iom1_i2c: i2c@40051000 {
184			reg = <0x40051000 0x1000>;
185			#address-cells = <1>;
186			#size-cells = <0>;
187			interrupts = <7 0>;
188			status = "disabled";
189			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
190		};
191
192		iom2_spi: spi@40052000 {
193			reg = <0x40052000 0x1000>;
194			#address-cells = <1>;
195			#size-cells = <0>;
196			interrupts = <8 0>;
197			status = "disabled";
198			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
199		};
200
201		iom2_i2c: i2c@40052000 {
202			reg = <0x40052000 0x1000>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			interrupts = <8 0>;
206			status = "disabled";
207			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
208		};
209
210		iom3_spi: spi@40053000 {
211			reg = <0x40053000 0x1000>;
212			#address-cells = <1>;
213			#size-cells = <0>;
214			interrupts = <9 0>;
215			status = "disabled";
216			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
217		};
218
219		iom3_i2c: i2c@40053000 {
220			reg = <0x40053000 0x1000>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			interrupts = <9 0>;
224			status = "disabled";
225			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
226		};
227
228		iom4_spi: spi@40054000 {
229			reg = <0x40054000 0x1000>;
230			#address-cells = <1>;
231			#size-cells = <0>;
232			interrupts = <10 0>;
233			status = "disabled";
234			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
235		};
236
237		iom4_i2c: i2c@40054000 {
238			reg = <0x40054000 0x1000>;
239			#address-cells = <1>;
240			#size-cells = <0>;
241			interrupts = <10 0>;
242			status = "disabled";
243			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
244		};
245
246		iom5_spi: spi@40055000 {
247			reg = <0x40055000 0x1000>;
248			#address-cells = <1>;
249			#size-cells = <0>;
250			interrupts = <11 0>;
251			status = "disabled";
252			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
253		};
254
255		iom5_i2c: i2c@40055000 {
256			reg = <0x40055000 0x1000>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			interrupts = <11 0>;
260			status = "disabled";
261			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
262		};
263
264		iom6_spi: spi@40056000 {
265			reg = <0x40056000 0x1000>;
266			#address-cells = <1>;
267			#size-cells = <0>;
268			interrupts = <12 0>;
269			status = "disabled";
270			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
271		};
272
273		iom6_i2c: i2c@40056000 {
274			reg = <0x40056000 0x1000>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			interrupts = <12 0>;
278			status = "disabled";
279			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
280		};
281
282		iom7_spi: spi@40057000 {
283			reg = <0x40057000 0x1000>;
284			#address-cells = <1>;
285			#size-cells = <0>;
286			interrupts = <13 0>;
287			status = "disabled";
288			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
289		};
290
291		iom7_i2c: i2c@40057000 {
292			reg = <0x40057000 0x1000>;
293			#address-cells = <1>;
294			#size-cells = <0>;
295			interrupts = <13 0>;
296			status = "disabled";
297			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
298		};
299
300		adc0: adc@40038000 {
301			reg = <0x40038000 0x400>;
302			interrupts = <19 0>;
303			interrupt-names = "ADC";
304			channel-count = <10>;
305			internal-vref-mv = <1190>;
306			status = "disabled";
307			#io-channel-cells = <1>;
308			ambiq,pwrcfg = <&pwrcfg 0x4 0x2000>;
309		};
310
311		mspi0: spi@40060000 {
312			compatible = "ambiq,mspi";
313			reg = <0x40060000 0x400>;
314			interrupts = <20 0>;
315			#address-cells = <1>;
316			#size-cells = <0>;
317			status = "disabled";
318			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
319		};
320
321		mspi1: spi@40061000 {
322			compatible = "ambiq,mspi";
323			reg = <0x40061000 0x400>;
324			interrupts = <21 0>;
325			#address-cells = <1>;
326			#size-cells = <0>;
327			status = "disabled";
328			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
329		};
330
331		mspi2: spi@40062000 {
332			compatible = "ambiq,mspi";
333			reg = <0x40062000 0x400>;
334			interrupts = <22 0>;
335			#address-cells = <1>;
336			#size-cells = <0>;
337			status = "disabled";
338			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
339		};
340
341		rtc0: rtc@40004800 {
342			compatible = "ambiq,rtc";
343			reg = <0x40004800 0x210>;
344			interrupts = <2 0>;
345			alarms-count = <1>;
346			status = "disabled";
347		};
348
349		usb: usb@400b0000 {
350			compatible = "ambiq,usb";
351			reg = <0x400B0000 0x4100>;
352			interrupts = <27 0>;
353			num-bidir-endpoints = <6>;
354			maximum-speed = "full-speed";
355			status = "disabled";
356			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
357		};
358
359		pinctrl: pin-controller@40010000 {
360			compatible = "ambiq,apollo4-pinctrl";
361			reg = <0x40010000 0x800>;
362			#address-cells = <1>;
363			#size-cells = <0>;
364
365			gpio: gpio@40010000 {
366				compatible = "ambiq,gpio";
367				gpio-map-mask = <0xffffffe0 0xffffffc0>;
368				gpio-map-pass-thru = <0x1f 0x3f>;
369				gpio-map = <
370					0x00 0x0 &gpio0_31 0x0 0x0
371					0x20 0x0 &gpio32_63 0x0 0x0
372					0x40 0x0 &gpio64_95 0x0 0x0
373					0x60 0x0 &gpio96_127 0x0 0x0
374				>;
375				reg = <0x40010000>;
376				#gpio-cells = <2>;
377				#address-cells = <1>;
378				#size-cells = <0>;
379				ranges;
380
381				gpio0_31: gpio0_31@0 {
382					compatible = "ambiq,gpio-bank";
383					gpio-controller;
384					#gpio-cells = <2>;
385					reg = <0>;
386					interrupts = <56 0>;
387					status = "disabled";
388				};
389
390				gpio32_63: gpio32_63@80 {
391					compatible = "ambiq,gpio-bank";
392					gpio-controller;
393					#gpio-cells = <2>;
394					reg = <0x80>;
395					interrupts = <57 0>;
396					status = "disabled";
397				};
398
399				gpio64_95: gpio64_95@100 {
400					compatible = "ambiq,gpio-bank";
401					gpio-controller;
402					#gpio-cells = <2>;
403					reg = <0x100>;
404					interrupts = <58 0>;
405					status = "disabled";
406				};
407
408				gpio96_127: gpio96_127@180 {
409					compatible = "ambiq,gpio-bank";
410					gpio-controller;
411					#gpio-cells = <2>;
412					reg = <0x180>;
413					interrupts = <59 0>;
414					status = "disabled";
415				};
416			};
417		};
418
419		wdt0: watchdog@40024000 {
420			compatible = "ambiq,watchdog";
421			reg = <0x40024000 0x400>;
422			interrupts = <1 0>;
423			clock-frequency = <16>;
424			status = "disabled";
425		};
426	};
427};
428
429&nvic {
430	arm,num-irq-priority-bits = <3>;
431};
432