Lines Matching +full:0 +full:x40024000
29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
57 #clock-cells = <0>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
80 reg = <0x40023c00 0x400>;
81 interrupts = <4 0>;
98 reg = <0x40023800 0x400>;
111 reg = <0x40013c00 0x400>;
113 interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
114 <10 0>, <23 0>, <40 0>;
117 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
125 reg = <0x40020000 0x2000>;
131 reg = <0x40020000 0x400>;
132 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
139 reg = <0x40020400 0x400>;
147 reg = <0x40020800 0x400>;
155 reg = <0x40020c00 0x400>;
163 reg = <0x40021000 0x400>;
171 reg = <0x40021400 0x400>;
179 reg = <0x40021800 0x400>;
187 reg = <0x40021c00 0x400>;
195 reg = <0x40022000 0x400>;
202 reg = <0x40002800 0x400>;
204 interrupts = <41 0>;
219 reg = <0x40003000 0x400>;
225 reg = <0x40002C00 0x400>;
227 interrupts = <0 7>;
233 reg = <0x40011000 0x400>;
236 interrupts = <37 0>;
242 reg = <0x40004400 0x400>;
245 interrupts = <38 0>;
251 reg = <0x40004800 0x400>;
254 interrupts = <39 0>;
260 reg = <0x40011400 0x400>;
263 interrupts = <71 0>;
269 reg = <0x40004c00 0x400>;
272 interrupts = <52 0>;
278 reg = <0x40005000 0x400>;
281 interrupts = <53 0>;
288 #size-cells = <0>;
289 reg = <0x40013000 0x400>;
298 #size-cells = <0>;
299 reg = <0x40003800 0x400>;
308 #size-cells = <0>;
309 reg = <0x40003c00 0x400>;
319 #size-cells = <0>;
320 reg = <0x40005400 0x400>;
322 interrupts = <31 0>, <32 0>;
331 #size-cells = <0>;
332 reg = <0x40005800 0x400>;
334 interrupts = <33 0>, <34 0>;
343 #size-cells = <0>;
344 reg = <0x40005c00 0x400>;
346 interrupts = <72 0>, <73 0>;
353 reg = <0x50000000 0x40000>;
354 interrupts = <67 0>;
367 reg = <0x40012000 0x400>;
369 interrupts = <18 0>;
372 resolutions = <STM32_ADC_RES(12, 0x00)
373 STM32_ADC_RES(10, 0x01)
374 STM32_ADC_RES(8, 0x02)
375 STM32_ADC_RES(6, 0x03)>;
385 reg = <0x40026000 0x400>;
386 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
394 reg = <0x40026400 0x400>;
395 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
403 reg = <0x40007400 0x400>;
411 reg = <0x40010000 0x400>;
412 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
413 resets = <&rctl STM32_RESET(APB2, 0U)>;
414 interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
416 st,prescaler = <0>;
428 reg = <0x40000000 0x400>;
429 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
430 resets = <&rctl STM32_RESET(APB1, 0U)>;
431 interrupts = <28 0>;
433 st,prescaler = <0>;
445 reg = <0x40000400 0x400>;
448 interrupts = <29 0>;
450 st,prescaler = <0>;
467 reg = <0x40000800 0x400>;
470 interrupts = <30 0>;
472 st,prescaler = <0>;
489 reg = <0x40000c00 0x400>;
492 interrupts = <50 0>;
494 st,prescaler = <0>;
511 reg = <0x40001000 0x400>;
514 interrupts = <54 0>;
516 st,prescaler = <0>;
527 reg = <0x40001400 0x400>;
530 interrupts = <55 0>;
532 st,prescaler = <0>;
543 reg = <0x40010400 0x400>;
546 interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
548 st,prescaler = <0>;
560 reg = <0x40014000 0x400>;
563 interrupts = <24 0>;
565 st,prescaler = <0>;
582 reg = <0x40014400 0x400>;
585 interrupts = <25 0>;
587 st,prescaler = <0>;
604 reg = <0x40014800 0x400>;
607 interrupts = <26 0>;
609 st,prescaler = <0>;
626 reg = <0x40001800 0x400>;
629 interrupts = <43 0>;
631 st,prescaler = <0>;
648 reg = <0x40001c00 0x400>;
651 interrupts = <44 0>;
653 st,prescaler = <0>;
670 reg = <0x40002000 0x400>;
673 interrupts = <45 0>;
675 st,prescaler = <0>;
692 reg = <0x50060800 0x400>;
693 interrupts = <80 0>;
700 reg = <0x40024000 DT_SIZE_K(4)>;
717 #phy-cells = <0>;
723 #size-cells = <0>;
731 #size-cells = <0>;
739 #size-cells = <0>;