1/* 2 * Copyright (c) 2018 qianfan Zhao 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9#include <arm/armv7-m.dtsi> 10#include <zephyr/dt-bindings/clock/stm32f4_clock.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 15#include <zephyr/dt-bindings/dma/stm32_dma.h> 16#include <zephyr/dt-bindings/adc/stm32f4_adc.h> 17#include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h> 18#include <zephyr/dt-bindings/adc/adc.h> 19#include <freq.h> 20 21/ { 22 chosen { 23 zephyr,entropy = &rng; 24 zephyr,flash-controller = &flash; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-m3"; 34 reg = <0>; 35 }; 36 }; 37 38 sram0: memory@20000000 { 39 compatible = "mmio-sram"; 40 }; 41 42 clocks { 43 clk_hse: clk-hse { 44 #clock-cells = <0>; 45 compatible = "st,stm32-hse-clock"; 46 status = "disabled"; 47 }; 48 49 clk_hsi: clk-hsi { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <DT_FREQ_M(16)>; 53 status = "disabled"; 54 }; 55 56 clk_lse: clk-lse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <32768>; 60 status = "disabled"; 61 }; 62 63 clk_lsi: clk-lsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <DT_FREQ_K(32)>; 67 status = "disabled"; 68 }; 69 70 pll: pll { 71 #clock-cells = <0>; 72 compatible = "st,stm32f2-pll-clock"; 73 status = "disabled"; 74 }; 75 }; 76 77 soc { 78 flash: flash-controller@40023c00 { 79 compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller"; 80 reg = <0x40023c00 0x400>; 81 interrupts = <4 0>; 82 83 #address-cells = <1>; 84 #size-cells = <1>; 85 86 flash0: flash@8000000 { 87 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 88 89 write-block-size = <1>; 90 /* maximum erase time(ms) for a 128K sector */ 91 max-erase-time = <4000>; 92 }; 93 }; 94 95 rcc: rcc@40023800 { 96 compatible = "st,stm32-rcc"; 97 #clock-cells = <2>; 98 reg = <0x40023800 0x400>; 99 100 rctl: reset-controller { 101 compatible = "st,stm32-rcc-rctl"; 102 #reset-cells = <1>; 103 }; 104 }; 105 106 exti: interrupt-controller@40013c00 { 107 compatible = "st,stm32-exti"; 108 interrupt-controller; 109 #interrupt-cells = <1>; 110 #address-cells = <1>; 111 reg = <0x40013c00 0x400>; 112 num-lines = <16>; 113 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 114 <10 0>, <23 0>, <40 0>; 115 interrupt-names = "line0", "line1", "line2", "line3", 116 "line4", "line5-9", "line10-15"; 117 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 118 <4 1>, <5 5>, <10 6>; 119 }; 120 121 pinctrl: pin-controller@40020000 { 122 compatible = "st,stm32-pinctrl"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 reg = <0x40020000 0x2000>; 126 127 gpioa: gpio@40020000 { 128 compatible = "st,stm32-gpio"; 129 gpio-controller; 130 #gpio-cells = <2>; 131 reg = <0x40020000 0x400>; 132 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 133 }; 134 135 gpiob: gpio@40020400 { 136 compatible = "st,stm32-gpio"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 reg = <0x40020400 0x400>; 140 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 141 }; 142 143 gpioc: gpio@40020800 { 144 compatible = "st,stm32-gpio"; 145 gpio-controller; 146 #gpio-cells = <2>; 147 reg = <0x40020800 0x400>; 148 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 149 }; 150 151 gpiod: gpio@40020c00 { 152 compatible = "st,stm32-gpio"; 153 gpio-controller; 154 #gpio-cells = <2>; 155 reg = <0x40020c00 0x400>; 156 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; 157 }; 158 159 gpioe: gpio@40021000 { 160 compatible = "st,stm32-gpio"; 161 gpio-controller; 162 #gpio-cells = <2>; 163 reg = <0x40021000 0x400>; 164 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; 165 }; 166 167 gpiof: gpio@40021400 { 168 compatible = "st,stm32-gpio"; 169 gpio-controller; 170 #gpio-cells = <2>; 171 reg = <0x40021400 0x400>; 172 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 173 }; 174 175 gpiog: gpio@40021800 { 176 compatible = "st,stm32-gpio"; 177 gpio-controller; 178 #gpio-cells = <2>; 179 reg = <0x40021800 0x400>; 180 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; 181 }; 182 183 gpioh: gpio@40021c00 { 184 compatible = "st,stm32-gpio"; 185 gpio-controller; 186 #gpio-cells = <2>; 187 reg = <0x40021c00 0x400>; 188 clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; 189 }; 190 191 gpioi: gpio@40022000 { 192 compatible = "st,stm32-gpio"; 193 gpio-controller; 194 #gpio-cells = <2>; 195 reg = <0x40022000 0x400>; 196 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; 197 }; 198 }; 199 200 rtc: rtc@40002800 { 201 compatible = "st,stm32-rtc"; 202 reg = <0x40002800 0x400>; 203 clocks = <&rcc STM32_CLOCK(APB1, 28U)>; 204 interrupts = <41 0>; 205 prescaler = <32768>; 206 alarms-count = <2>; 207 alrm-exti-line = <17>; 208 status = "disabled"; 209 210 bbram: backup_regs { 211 compatible = "st,stm32-bbram"; 212 st,backup-regs = <20>; 213 status = "disabled"; 214 }; 215 }; 216 217 iwdg: watchdog@40003000 { 218 compatible = "st,stm32-watchdog"; 219 reg = <0x40003000 0x400>; 220 status = "disabled"; 221 }; 222 223 wwdg: watchdog@40002c00 { 224 compatible = "st,stm32-window-watchdog"; 225 reg = <0x40002C00 0x400>; 226 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 227 interrupts = <0 7>; 228 status = "disabled"; 229 }; 230 231 usart1: serial@40011000 { 232 compatible = "st,stm32-usart", "st,stm32-uart"; 233 reg = <0x40011000 0x400>; 234 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 235 resets = <&rctl STM32_RESET(APB2, 4U)>; 236 interrupts = <37 0>; 237 status = "disabled"; 238 }; 239 240 usart2: serial@40004400 { 241 compatible = "st,stm32-usart", "st,stm32-uart"; 242 reg = <0x40004400 0x400>; 243 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 244 resets = <&rctl STM32_RESET(APB1, 17U)>; 245 interrupts = <38 0>; 246 status = "disabled"; 247 }; 248 249 usart3: serial@40004800 { 250 compatible = "st,stm32-usart", "st,stm32-uart"; 251 reg = <0x40004800 0x400>; 252 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 253 resets = <&rctl STM32_RESET(APB1, 18U)>; 254 interrupts = <39 0>; 255 status = "disabled"; 256 }; 257 258 usart6: serial@40011400 { 259 compatible = "st,stm32-usart", "st,stm32-uart"; 260 reg = <0x40011400 0x400>; 261 clocks = <&rcc STM32_CLOCK(APB2, 5U)>; 262 resets = <&rctl STM32_RESET(APB2, 5U)>; 263 interrupts = <71 0>; 264 status = "disabled"; 265 }; 266 267 uart4: serial@40004c00 { 268 compatible ="st,stm32-uart"; 269 reg = <0x40004c00 0x400>; 270 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 271 resets = <&rctl STM32_RESET(APB1, 19U)>; 272 interrupts = <52 0>; 273 status = "disabled"; 274 }; 275 276 uart5: serial@40005000 { 277 compatible = "st,stm32-uart"; 278 reg = <0x40005000 0x400>; 279 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 280 resets = <&rctl STM32_RESET(APB1, 20U)>; 281 interrupts = <53 0>; 282 status = "disabled"; 283 }; 284 285 spi1: spi@40013000 { 286 compatible = "st,stm32-spi"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0x40013000 0x400>; 290 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 291 interrupts = <35 5>; 292 status = "disabled"; 293 }; 294 295 spi2: spi@40003800 { 296 compatible = "st,stm32-spi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x40003800 0x400>; 300 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 301 interrupts = <36 5>; 302 status = "disabled"; 303 }; 304 305 spi3: spi@40003c00 { 306 compatible = "st,stm32-spi"; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x40003c00 0x400>; 310 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 311 interrupts = <51 5>; 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@40005400 { 316 compatible = "st,stm32-i2c-v1"; 317 clock-frequency = <I2C_BITRATE_STANDARD>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x40005400 0x400>; 321 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 322 interrupts = <31 0>, <32 0>; 323 interrupt-names = "event", "error"; 324 status = "disabled"; 325 }; 326 327 i2c2: i2c@40005800 { 328 compatible = "st,stm32-i2c-v1"; 329 clock-frequency = <I2C_BITRATE_STANDARD>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0x40005800 0x400>; 333 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 334 interrupts = <33 0>, <34 0>; 335 interrupt-names = "event", "error"; 336 status = "disabled"; 337 }; 338 339 i2c3: i2c@40005c00 { 340 compatible = "st,stm32-i2c-v1"; 341 clock-frequency = <I2C_BITRATE_STANDARD>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 reg = <0x40005c00 0x400>; 345 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 346 interrupts = <72 0>, <73 0>; 347 interrupt-names = "event", "error"; 348 status = "disabled"; 349 }; 350 351 usbotg_fs: usb@50000000 { 352 compatible = "st,stm32-otgfs"; 353 reg = <0x50000000 0x40000>; 354 interrupts = <67 0>; 355 interrupt-names = "otgfs"; 356 num-bidir-endpoints = <4>; 357 ram-size = <1280>; 358 maximum-speed = "full-speed"; 359 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, 360 <&rcc STM32_SRC_PLL_Q NO_SEL>; 361 phys = <&otgfs_phy>; 362 status = "disabled"; 363 }; 364 365 adc1: adc@40012000 { 366 compatible = "st,stm32f4-adc", "st,stm32-adc"; 367 reg = <0x40012000 0x400>; 368 clocks = <&rcc STM32_CLOCK(APB2, 8U)>; 369 interrupts = <18 0>; 370 status = "disabled"; 371 #io-channel-cells = <1>; 372 resolutions = <STM32_ADC_RES(12, 0x00) 373 STM32_ADC_RES(10, 0x01) 374 STM32_ADC_RES(8, 0x02) 375 STM32_ADC_RES(6, 0x03)>; 376 sampling-times = <3 15 28 58 84 112 144 480>; 377 st,adc-clock-source = "SYNC"; 378 st,adc-sequencer = "FULLY_CONFIGURABLE"; 379 st,adc-oversampler = "OVERSAMPLER_NONE"; 380 }; 381 382 dma1: dma@40026000 { 383 compatible = "st,stm32-dma-v1"; 384 #dma-cells = <4>; 385 reg = <0x40026000 0x400>; 386 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; 387 clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; 388 status = "disabled"; 389 }; 390 391 dma2: dma@40026400 { 392 compatible = "st,stm32-dma-v1"; 393 #dma-cells = <4>; 394 reg = <0x40026400 0x400>; 395 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; 396 clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; 397 st,mem2mem; 398 status = "disabled"; 399 }; 400 401 dac1: dac@40007400 { 402 compatible = "st,stm32-dac"; 403 reg = <0x40007400 0x400>; 404 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 405 status = "disabled"; 406 #io-channel-cells = <1>; 407 }; 408 409 timers1: timers@40010000 { 410 compatible = "st,stm32-timers"; 411 reg = <0x40010000 0x400>; 412 clocks = <&rcc STM32_CLOCK(APB2, 0U)>; 413 resets = <&rctl STM32_RESET(APB2, 0U)>; 414 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 415 interrupt-names = "brk", "up", "trgcom", "cc"; 416 st,prescaler = <0>; 417 status = "disabled"; 418 419 pwm { 420 compatible = "st,stm32-pwm"; 421 status = "disabled"; 422 #pwm-cells = <3>; 423 }; 424 }; 425 426 timers2: timers@40000000 { 427 compatible = "st,stm32-timers"; 428 reg = <0x40000000 0x400>; 429 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 430 resets = <&rctl STM32_RESET(APB1, 0U)>; 431 interrupts = <28 0>; 432 interrupt-names = "global"; 433 st,prescaler = <0>; 434 status = "disabled"; 435 436 pwm { 437 compatible = "st,stm32-pwm"; 438 status = "disabled"; 439 #pwm-cells = <3>; 440 }; 441 }; 442 443 timers3: timers@40000400 { 444 compatible = "st,stm32-timers"; 445 reg = <0x40000400 0x400>; 446 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 447 resets = <&rctl STM32_RESET(APB1, 1U)>; 448 interrupts = <29 0>; 449 interrupt-names = "global"; 450 st,prescaler = <0>; 451 status = "disabled"; 452 453 pwm { 454 compatible = "st,stm32-pwm"; 455 status = "disabled"; 456 #pwm-cells = <3>; 457 }; 458 459 counter { 460 compatible = "st,stm32-counter"; 461 status = "disabled"; 462 }; 463 }; 464 465 timers4: timers@40000800 { 466 compatible = "st,stm32-timers"; 467 reg = <0x40000800 0x400>; 468 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 469 resets = <&rctl STM32_RESET(APB1, 2U)>; 470 interrupts = <30 0>; 471 interrupt-names = "global"; 472 st,prescaler = <0>; 473 status = "disabled"; 474 475 pwm { 476 compatible = "st,stm32-pwm"; 477 status = "disabled"; 478 #pwm-cells = <3>; 479 }; 480 481 counter { 482 compatible = "st,stm32-counter"; 483 status = "disabled"; 484 }; 485 }; 486 487 timers5: timers@40000c00 { 488 compatible = "st,stm32-timers"; 489 reg = <0x40000c00 0x400>; 490 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 491 resets = <&rctl STM32_RESET(APB1, 3U)>; 492 interrupts = <50 0>; 493 interrupt-names = "global"; 494 st,prescaler = <0>; 495 status = "disabled"; 496 497 pwm { 498 compatible = "st,stm32-pwm"; 499 status = "disabled"; 500 #pwm-cells = <3>; 501 }; 502 503 counter { 504 compatible = "st,stm32-counter"; 505 status = "disabled"; 506 }; 507 }; 508 509 timers6: timers@40001000 { 510 compatible = "st,stm32-timers"; 511 reg = <0x40001000 0x400>; 512 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 513 resets = <&rctl STM32_RESET(APB1, 4U)>; 514 interrupts = <54 0>; 515 interrupt-names = "global"; 516 st,prescaler = <0>; 517 status = "disabled"; 518 519 counter { 520 compatible = "st,stm32-counter"; 521 status = "disabled"; 522 }; 523 }; 524 525 timers7: timers@40001400 { 526 compatible = "st,stm32-timers"; 527 reg = <0x40001400 0x400>; 528 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 529 resets = <&rctl STM32_RESET(APB1, 5U)>; 530 interrupts = <55 0>; 531 interrupt-names = "global"; 532 st,prescaler = <0>; 533 status = "disabled"; 534 535 counter { 536 compatible = "st,stm32-counter"; 537 status = "disabled"; 538 }; 539 }; 540 541 timers8: timers@40010400 { 542 compatible = "st,stm32-timers"; 543 reg = <0x40010400 0x400>; 544 clocks = <&rcc STM32_CLOCK(APB2, 1U)>; 545 resets = <&rctl STM32_RESET(APB2, 1U)>; 546 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 547 interrupt-names = "brk", "up", "trgcom", "cc"; 548 st,prescaler = <0>; 549 status = "disabled"; 550 551 pwm { 552 compatible = "st,stm32-pwm"; 553 status = "disabled"; 554 #pwm-cells = <3>; 555 }; 556 }; 557 558 timers9: timers@40014000 { 559 compatible = "st,stm32-timers"; 560 reg = <0x40014000 0x400>; 561 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 562 resets = <&rctl STM32_RESET(APB2, 16U)>; 563 interrupts = <24 0>; 564 interrupt-names = "global"; 565 st,prescaler = <0>; 566 status = "disabled"; 567 568 pwm { 569 compatible = "st,stm32-pwm"; 570 status = "disabled"; 571 #pwm-cells = <3>; 572 }; 573 574 counter { 575 compatible = "st,stm32-counter"; 576 status = "disabled"; 577 }; 578 }; 579 580 timers10: timers@40014400 { 581 compatible = "st,stm32-timers"; 582 reg = <0x40014400 0x400>; 583 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 584 resets = <&rctl STM32_RESET(APB2, 17U)>; 585 interrupts = <25 0>; 586 interrupt-names = "global"; 587 st,prescaler = <0>; 588 status = "disabled"; 589 590 pwm { 591 compatible = "st,stm32-pwm"; 592 status = "disabled"; 593 #pwm-cells = <3>; 594 }; 595 596 counter { 597 compatible = "st,stm32-counter"; 598 status = "disabled"; 599 }; 600 }; 601 602 timers11: timers@40014800 { 603 compatible = "st,stm32-timers"; 604 reg = <0x40014800 0x400>; 605 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 606 resets = <&rctl STM32_RESET(APB2, 18U)>; 607 interrupts = <26 0>; 608 interrupt-names = "global"; 609 st,prescaler = <0>; 610 status = "disabled"; 611 612 pwm { 613 compatible = "st,stm32-pwm"; 614 status = "disabled"; 615 #pwm-cells = <3>; 616 }; 617 618 counter { 619 compatible = "st,stm32-counter"; 620 status = "disabled"; 621 }; 622 }; 623 624 timers12: timers@40001800 { 625 compatible = "st,stm32-timers"; 626 reg = <0x40001800 0x400>; 627 clocks = <&rcc STM32_CLOCK(APB1, 6U)>; 628 resets = <&rctl STM32_RESET(APB1, 6U)>; 629 interrupts = <43 0>; 630 interrupt-names = "global"; 631 st,prescaler = <0>; 632 status = "disabled"; 633 634 pwm { 635 compatible = "st,stm32-pwm"; 636 status = "disabled"; 637 #pwm-cells = <3>; 638 }; 639 640 counter { 641 compatible = "st,stm32-counter"; 642 status = "disabled"; 643 }; 644 }; 645 646 timers13: timers@40001c00 { 647 compatible = "st,stm32-timers"; 648 reg = <0x40001c00 0x400>; 649 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 650 resets = <&rctl STM32_RESET(APB1, 7U)>; 651 interrupts = <44 0>; 652 interrupt-names = "global"; 653 st,prescaler = <0>; 654 status = "disabled"; 655 656 pwm { 657 compatible = "st,stm32-pwm"; 658 status = "disabled"; 659 #pwm-cells = <3>; 660 }; 661 662 counter { 663 compatible = "st,stm32-counter"; 664 status = "disabled"; 665 }; 666 }; 667 668 timers14: timers@40002000 { 669 compatible = "st,stm32-timers"; 670 reg = <0x40002000 0x400>; 671 clocks = <&rcc STM32_CLOCK(APB1, 8U)>; 672 resets = <&rctl STM32_RESET(APB1, 8U)>; 673 interrupts = <45 0>; 674 interrupt-names = "global"; 675 st,prescaler = <0>; 676 status = "disabled"; 677 678 pwm { 679 compatible = "st,stm32-pwm"; 680 status = "disabled"; 681 #pwm-cells = <3>; 682 }; 683 684 counter { 685 compatible = "st,stm32-counter"; 686 status = "disabled"; 687 }; 688 }; 689 690 rng: rng@50060800 { 691 compatible = "st,stm32-rng"; 692 reg = <0x50060800 0x400>; 693 interrupts = <80 0>; 694 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 695 status = "disabled"; 696 }; 697 698 backup_sram: memory@40024000 { 699 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 700 reg = <0x40024000 DT_SIZE_K(4)>; 701 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; 702 zephyr,memory-region = "BACKUP_SRAM"; 703 status = "disabled"; 704 }; 705 }; 706 707 die_temp: dietemp { 708 compatible = "st,stm32-temp"; 709 io-channels = <&adc1 16>; 710 status = "disabled"; 711 avgslope = "2.5"; 712 v25 = <760>; 713 }; 714 715 otgfs_phy: otgfs_phy { 716 compatible = "usb-nop-xceiv"; 717 #phy-cells = <0>; 718 }; 719 720 smbus1: smbus1 { 721 compatible = "st,stm32-smbus"; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 i2c = <&i2c1>; 725 status = "disabled"; 726 }; 727 728 smbus2: smbus2 { 729 compatible = "st,stm32-smbus"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 i2c = <&i2c2>; 733 status = "disabled"; 734 }; 735 736 smbus3: smbus3 { 737 compatible = "st,stm32-smbus"; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 i2c = <&i2c3>; 741 status = "disabled"; 742 }; 743}; 744 745&nvic { 746 arm,num-irq-priority-bits = <4>; 747}; 748
