1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/adc/adc.h>
7#include <zephyr/dt-bindings/i2c/i2c.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	clocks {
12		uartclk: apb-pclk {
13			compatible = "fixed-clock";
14			clock-frequency = <DT_FREQ_M(24)>;
15			#clock-cells = <0>;
16		};
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			cpu-power-states = <&idle &suspend_to_ram>;
27			#address-cells = <1>;
28			#size-cells = <1>;
29
30			itm: itm@e0000000 {
31				compatible = "arm,armv7m-itm";
32				reg = <0xe0000000 0x1000>;
33				swo-ref-frequency = <DT_FREQ_M(6)>;
34			};
35		};
36
37		power-states {
38			idle: idle {
39				compatible = "zephyr,power-state";
40				power-state-name = "suspend-to-idle";
41				/* As Apollo3blueplus datasheet, run_to_sleep and sleep_to_run
42				 * transition time are both lower than 1us, but considering
43				 * the software overhead we set a bigger value.
44				 */
45				min-residency-us = <100>;
46				exit-latency-us = <5>;
47			};
48
49			suspend_to_ram: suspend_to_ram {
50				compatible = "zephyr,power-state";
51				power-state-name = "suspend-to-ram";
52				/* As Apollo3blueplus datasheet, run_to_deepsleep transition time
53				 * is the software overhead 1us and deepsleep_to_run transition
54				 * time is about 25us,but considering the software overhead,
55				 * we set a bigger value.
56				 */
57				min-residency-us = <2000>;
58				exit-latency-us = <125>;
59			};
60		};
61	};
62
63	/* TCM */
64	tcm: tcm@10000000 {
65		compatible = "zephyr,memory-region";
66		reg = <0x10000000 0x10000>;
67		zephyr,memory-region = "ITCM";
68	};
69
70	/* SRAM */
71	sram0: memory@10010000 {
72		compatible = "mmio-sram";
73		reg = <0x10010000 0xB0000>;
74	};
75
76	xip0: memory@52000000 {
77		compatible = "zephyr,memory-region";
78		reg = <0x52000000 0x2000000>;
79		zephyr,memory-region = "XIP0";
80	};
81
82	xip1: memory@54000000 {
83		compatible = "zephyr,memory-region";
84		reg = <0x54000000 0x2000000>;
85		zephyr,memory-region = "XIP1";
86	};
87
88	xip2: memory@56000000 {
89		compatible = "zephyr,memory-region";
90		reg = <0x56000000 0x2000000>;
91		zephyr,memory-region = "XIP2";
92	};
93
94	soc {
95		compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
96
97		flash: flash-controller@c000 {
98			compatible = "ambiq,flash-controller";
99			reg = <0x0000c000 0x1f4000>;
100
101			#address-cells = <1>;
102			#size-cells = <1>;
103
104			/* Flash region */
105			flash0: flash@c000 {
106				compatible = "soc-nv-flash";
107				reg = <0x0000c000 0x1f4000>;
108			};
109		};
110
111		pwrcfg: pwrcfg@40021000 {
112			compatible = "ambiq,pwrctrl";
113			reg = <0x40021000 0x400>;
114			#pwrcfg-cells = <2>;
115		};
116
117		stimer0: stimer@40008140 {
118			compatible = "ambiq,stimer";
119			reg = <0x40008140 0x80>;
120			interrupts = <23 0>;
121			status = "okay";
122		};
123
124		counter0: counter@40008000 {
125			compatible = "ambiq,counter";
126			reg = <0x40008000 0x20>;
127			interrupts = <14 0>;
128			clock-frequency = <DT_FREQ_M(3)>;
129			clk-source = <2>;
130			status = "disabled";
131		};
132
133		counter1: counter@40008020 {
134			compatible = "ambiq,counter";
135			reg = <0x40008020 0x20>;
136			interrupts = <14 0>;
137			clock-frequency = <DT_FREQ_M(3)>;
138			clk-source = <2>;
139			status = "disabled";
140		};
141
142		counter2: counter@40008040 {
143			compatible = "ambiq,counter";
144			reg = <0x40008040 0x20>;
145			interrupts = <14 0>;
146			clock-frequency = <DT_FREQ_M(3)>;
147			clk-source = <2>;
148			status = "disabled";
149		};
150
151		counter3: counter@40008060 {
152			compatible = "ambiq,counter";
153			reg = <0x40008060 0x20>;
154			interrupts = <14 0>;
155			clock-frequency = <DT_FREQ_M(3)>;
156			clk-source = <2>;
157			status = "disabled";
158		};
159
160		counter4: counter@40008080 {
161			compatible = "ambiq,counter";
162			reg = <0x40008080 0x20>;
163			interrupts = <14 0>;
164			clock-frequency = <DT_FREQ_M(3)>;
165			clk-source = <2>;
166			status = "disabled";
167		};
168
169		counter5: counter@400080a0 {
170			compatible = "ambiq,counter";
171			reg = <0x400080A0 0x20>;
172			interrupts = <14 0>;
173			clock-frequency = <DT_FREQ_M(3)>;
174			clk-source = <2>;
175			status = "disabled";
176		};
177
178		counter6: counter@400080c0 {
179			compatible = "ambiq,counter";
180			reg = <0x400080C0 0x20>;
181			interrupts = <14 0>;
182			clock-frequency = <DT_FREQ_M(3)>;
183			clk-source = <2>;
184			status = "disabled";
185		};
186
187		counter7: counter@400080e0 {
188			compatible = "ambiq,counter";
189			reg = <0x400080E0 0x20>;
190			interrupts = <14 0>;
191			clock-frequency = <DT_FREQ_M(3)>;
192			clk-source = <2>;
193			status = "disabled";
194		};
195
196		uart0: uart@4001c000 {
197			compatible = "ambiq,uart", "arm,pl011";
198			reg = <0x4001c000 0x1000>;
199			interrupts = <15 0>;
200			interrupt-names = "UART0";
201			status = "disabled";
202			clocks = <&uartclk>;
203			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
204			zephyr,pm-device-runtime-auto;
205		};
206
207		uart1: uart@4001d000 {
208			compatible = "ambiq,uart", "arm,pl011";
209			reg = <0x4001d000 0x1000>;
210			interrupts = <16 0>;
211			interrupt-names = "UART1";
212			status = "disabled";
213			clocks = <&uartclk>;
214			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
215			zephyr,pm-device-runtime-auto;
216		};
217
218		spid0: spi@50000100 {
219			compatible = "ambiq,spid";
220			reg = <0x50000100 0x1000>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			interrupts = <4 0>;
224			status = "disabled";
225			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
226			zephyr,pm-device-runtime-auto;
227		};
228
229		spi0: spi@50004000 {
230			reg = <0x50004000 0x1000>;
231			#address-cells = <1>;
232			#size-cells = <0>;
233			interrupts = <6 0>;
234			status = "disabled";
235			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
236			zephyr,pm-device-runtime-auto;
237		};
238
239		spi1: spi@50005000 {
240			reg = <0x50005000 0x1000>;
241			#address-cells = <1>;
242			#size-cells = <0>;
243			interrupts = <7 0>;
244			status = "disabled";
245			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
246			zephyr,pm-device-runtime-auto;
247		};
248
249		spi2: spi@50006000 {
250			reg = <0x50006000 0x1000>;
251			#address-cells = <1>;
252			#size-cells = <0>;
253			interrupts = <8 0>;
254			status = "disabled";
255			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
256			zephyr,pm-device-runtime-auto;
257		};
258
259		spi3: spi@50007000 {
260			reg = <0x50007000 0x1000>;
261			#address-cells = <1>;
262			#size-cells = <0>;
263			interrupts = <9 0>;
264			status = "disabled";
265			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
266			zephyr,pm-device-runtime-auto;
267		};
268
269		spi4: spi@50008000 {
270			reg = <0x50008000 0x1000>;
271			#address-cells = <1>;
272			#size-cells = <0>;
273			interrupts = <10 0>;
274			status = "disabled";
275			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
276			zephyr,pm-device-runtime-auto;
277		};
278
279		spi5: spi@50009000 {
280			reg = <0x50009000 0x1000>;
281			#address-cells = <1>;
282			#size-cells = <0>;
283			interrupts = <11 0>;
284			status = "disabled";
285			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
286			zephyr,pm-device-runtime-auto;
287		};
288
289		i2c0: i2c@50004000 {
290			reg = <0x50004000 0x1000>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293			interrupts = <6 0>;
294			status = "disabled";
295			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
296			zephyr,pm-device-runtime-auto;
297		};
298
299		i2c1: i2c@50005000 {
300			reg = <0x50005000 0x1000>;
301			#address-cells = <1>;
302			#size-cells = <0>;
303			interrupts = <7 0>;
304			status = "disabled";
305			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
306			zephyr,pm-device-runtime-auto;
307		};
308
309		i2c2: i2c@50006000 {
310			reg = <0x50006000 0x1000>;
311			#address-cells = <1>;
312			#size-cells = <0>;
313			interrupts = <8 0>;
314			status = "disabled";
315			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
316			zephyr,pm-device-runtime-auto;
317		};
318
319		i2c3: i2c@50007000 {
320			reg = <0x50007000 0x1000>;
321			#address-cells = <1>;
322			#size-cells = <0>;
323			interrupts = <9 0>;
324			status = "disabled";
325			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
326			zephyr,pm-device-runtime-auto;
327		};
328
329		i2c4: i2c@50008000 {
330			reg = <0x50008000 0x1000>;
331			#address-cells = <1>;
332			#size-cells = <0>;
333			interrupts = <10 0>;
334			status = "disabled";
335			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
336			zephyr,pm-device-runtime-auto;
337		};
338
339		i2c5: i2c@50009000 {
340			reg = <0x50009000 0x1000>;
341			#address-cells = <1>;
342			#size-cells = <0>;
343			interrupts = <11 0>;
344			status = "disabled";
345			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
346			zephyr,pm-device-runtime-auto;
347		};
348
349		adc0: adc@50010000 {
350			reg = <0x50010000 0x400>;
351			interrupts = <18 0>;
352			interrupt-names = "ADC";
353			channel-count = <10>;
354			internal-vref-mv = <1500>;
355			status = "disabled";
356			#io-channel-cells = <1>;
357			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
358		};
359
360		mspi0: mspi@50014000 {
361			compatible = "ambiq,mspi-controller";
362			reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
363			clock-frequency = <48000000>;
364			interrupts = <20 0>;
365			#address-cells = <1>;
366			#size-cells = <0>;
367			status = "disabled";
368			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
369		};
370
371		mspi1: mspi@50015000 {
372			compatible = "ambiq,mspi-controller";
373			reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
374			clock-frequency = <48000000>;
375			interrupts = <32 0>;
376			#address-cells = <1>;
377			#size-cells = <0>;
378			status = "disabled";
379			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
380		};
381
382		mspi2: mspi@50016000 {
383			compatible = "ambiq,mspi-controller";
384			clock-frequency = <48000000>;
385			reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
386			interrupts = <33 0>;
387			#address-cells = <1>;
388			#size-cells = <0>;
389			status = "disabled";
390			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
391		};
392
393		rtc0: rtc@40004240 {
394			compatible = "ambiq,rtc";
395			reg = <0x40004240 0xD0>;
396			interrupts = <2 0>;
397			alarms-count = <1>;
398			status = "disabled";
399		};
400
401		bleif: spi@5000c000 {
402			compatible = "ambiq,spi-bleif";
403			reg = <0x5000c000 0x414>;
404			interrupts = <12 1>;
405			#address-cells = <1>;
406			#size-cells = <0>;
407			status = "disabled";
408			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
409
410			bt_hci_apollo: bt-hci@0 {
411				compatible = "ambiq,bt-hci-spi";
412				spi-max-frequency = <DT_FREQ_M(6)>;
413				reg = <0>;
414			};
415		};
416
417		pinctrl: pin-controller@40010000 {
418			compatible = "ambiq,apollo3-pinctrl";
419			reg = <0x40010000 0x800>;
420			#address-cells = <1>;
421			#size-cells = <0>;
422
423			gpio: gpio@40010000 {
424				compatible = "ambiq,gpio";
425				gpio-map-mask = <0xffffffe0 0xffffffc0>;
426				gpio-map-pass-thru = <0x1f 0x3f>;
427				gpio-map = <
428					0x00 0x0 &gpio0_31 0x0 0x0
429					0x20 0x0 &gpio32_63 0x0 0x0
430					0x40 0x0 &gpio64_95 0x0 0x0
431				>;
432				reg = <0x40010000>;
433				#gpio-cells = <2>;
434				#address-cells = <1>;
435				#size-cells = <0>;
436				ranges;
437
438				gpio0_31: gpio0_31@0 {
439					compatible = "ambiq,gpio-bank";
440					gpio-controller;
441					#gpio-cells = <2>;
442					reg = <0>;
443					interrupts = <13 0>;
444					status = "disabled";
445				};
446
447				gpio32_63: gpio32_63@20 {
448					compatible = "ambiq,gpio-bank";
449					gpio-controller;
450					#gpio-cells = <2>;
451					reg = <0x20>;
452					interrupts = <13 0>;
453					status = "disabled";
454				};
455
456				gpio64_95: gpio64_95@40 {
457					compatible = "ambiq,gpio-bank";
458					gpio-controller;
459					#gpio-cells = <2>;
460					reg = <0x40>;
461					interrupts = <13 0>;
462					status = "disabled";
463					ngpios = <10>;
464				};
465			};
466		};
467
468		wdt0: watchdog@40024000 {
469			compatible = "ambiq,watchdog";
470			reg = <0x40024000 0x400>;
471			interrupts = <1 0>;
472			clock-frequency = <16>;
473			status = "disabled";
474		};
475	};
476};
477
478&nvic {
479	arm,num-irq-priority-bits = <3>;
480};
481