Lines Matching +full:0 +full:x40024000
14 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0>;
40 reg = <0xe0000000 0x1000>;
49 reg = <0x10000000 0x10000>;
56 reg = <0x10010000 0x2B0000>;
64 reg = <0x00018000 0x1e8000>;
72 reg = <0x00018000 0x1e8000>;
78 reg = <0x40021000 0x400>;
84 reg = <0x40008800 0x80>;
85 interrupts = <32 0>;
91 reg = <0x40008200 0x20>;
92 interrupts = <67 0>;
100 reg = <0x4001c000 0x1000>;
101 interrupts = <15 0>;
105 ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
109 reg = <0x4001d000 0x1000>;
110 interrupts = <16 0>;
114 ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
119 reg = <0x4001e000 0x1000>;
120 interrupts = <17 0>;
124 ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
129 reg = <0x4001f000 0x1000>;
130 interrupts = <18 0>;
134 ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
138 reg = <0x40050000 0x1000>;
140 #size-cells = <0>;
141 interrupts = <6 0>;
143 ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
147 reg = <0x40051000 0x1000>;
149 #size-cells = <0>;
150 interrupts = <7 0>;
152 ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
156 reg = <0x40052000 0x1000>;
158 #size-cells = <0>;
159 interrupts = <8 0>;
161 ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
165 reg = <0x40053000 0x1000>;
167 #size-cells = <0>;
168 interrupts = <9 0>;
170 ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
176 reg = <0x40054000 0x1000>;
178 #size-cells = <0>;
179 interrupts = <10 0>;
183 ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
185 bt_hci_apollo: bt-hci@0 {
187 reg = <0>;
196 reg = <0x40055000 0x1000>;
198 #size-cells = <0>;
199 interrupts = <11 0>;
201 ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
205 reg = <0x40056000 0x1000>;
207 #size-cells = <0>;
208 interrupts = <12 0>;
210 ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
214 reg = <0x40057000 0x1000>;
216 #size-cells = <0>;
217 interrupts = <13 0>;
219 ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
223 reg = <0x40050000 0x1000>;
225 #size-cells = <0>;
226 interrupts = <6 0>;
228 ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
232 reg = <0x40051000 0x1000>;
234 #size-cells = <0>;
235 interrupts = <7 0>;
237 ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
241 reg = <0x40052000 0x1000>;
243 #size-cells = <0>;
244 interrupts = <8 0>;
246 ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
250 reg = <0x40053000 0x1000>;
252 #size-cells = <0>;
253 interrupts = <9 0>;
255 ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
259 reg = <0x40054000 0x1000>;
261 #size-cells = <0>;
262 interrupts = <10 0>;
264 ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
268 reg = <0x40055000 0x1000>;
270 #size-cells = <0>;
271 interrupts = <11 0>;
273 ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
277 reg = <0x40056000 0x1000>;
279 #size-cells = <0>;
280 interrupts = <12 0>;
282 ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
286 reg = <0x40057000 0x1000>;
288 #size-cells = <0>;
289 interrupts = <13 0>;
291 ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
296 reg = <0x40060000 0x400>;
297 interrupts = <20 0>;
299 #size-cells = <0>;
301 ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
306 reg = <0x40061000 0x400>;
307 interrupts = <21 0>;
309 #size-cells = <0>;
311 ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
316 reg = <0x40062000 0x400>;
317 interrupts = <22 0>;
319 #size-cells = <0>;
321 ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
326 reg = <0x400B0000 0x4100>;
327 interrupts = <27 0>;
331 ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
336 reg = <0x40004800 0x210>;
337 interrupts = <2 0>;
344 reg = <0x40010000 0x800>;
346 #size-cells = <0>;
350 gpio-map-mask = <0xffffffe0 0xffffffc0>;
351 gpio-map-pass-thru = <0x1f 0x3f>;
353 0x00 0x0 &gpio0_31 0x0 0x0
354 0x20 0x0 &gpio32_63 0x0 0x0
355 0x40 0x0 &gpio64_95 0x0 0x0
356 0x60 0x0 &gpio96_127 0x0 0x0
358 reg = <0x40010000>;
361 #size-cells = <0>;
364 gpio0_31: gpio0_31@0 {
368 reg = <0>;
369 interrupts = <56 0>;
377 reg = <0x80>;
378 interrupts = <57 0>;
386 reg = <0x100>;
387 interrupts = <58 0>;
395 reg = <0x180>;
396 interrupts = <59 0>;
404 reg = <0x40024000 0x400>;
405 interrupts = <1 0>;