Lines Matching +full:0 +full:x40024000
16 #size-cells = <0>;
18 cpu0: cpu@0 {
20 reg = <0>;
26 reg = <0x58001000 0x1400>;
38 #clock-cells = <0>;
44 reg = <0x40044000 0xff>, <0x50004800 0xff>;
54 reg = <0x48028000 0x1000>;
62 reg = <0x48028000 0x100>;
70 reg = <0x48028100 0x100>;
78 reg = <0x48028200 0x100>;
86 reg = <0x48028e00 0x100>;
94 reg = <0x48028f00 0x100>;
101 reg = <0x50014000 0x2bc>;
110 reg = <0x50018000 0x15c>;
118 reg = <0x40030000 0x1ff>;
124 reg = <0x40030200 0x1ff>;
130 reg = <0x48020000 0x1ff>;
136 reg = <0x48020200 0x1ff>;
142 reg = <0x48024000 0x1ff>;
148 reg = <0x48024200 0x1ff>;
155 reg = <0x40004400 0x400>;
163 reg = <0x40004800 0x400>;
171 reg = <0x40004C00 0x400>;
179 reg = <0x40005000 0x400>;
186 reg = <0x5000408c 0x8>;
193 reg = <0x4000c000 0x4000>;
200 reg = <0x40010000 0x4000>;
207 reg = <0x40014000 0x4000>;
214 reg = <0x48004000 0x4000>;
221 reg = <0x40020000 0x4000>;
228 reg = <0x40024000 0x4000>;
235 reg = <0x50008000 0x4000>;
236 interrupts = <0 1>; // shared interrupt line with rtc
242 reg = <0x50004a00 0x200>;
243 interrupts = <0 1>; // shared interrupt line with wdt0
249 reg = <0x5000C000 0x3FFF>;
261 #size-cells = <0>;
267 reg = <0x48014000 0x4000>;
275 reg = <0x48014200 0x100>;
282 reg = <0x48014300 0x100>;
289 reg = <0x48014400 0x100>;