Lines Matching +full:0 +full:x40024000
15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0x50000>;
79 flash: flash-controller@0 {
81 reg = <0x00000000 0x100000>;
87 flash0: flash@0 {
89 reg = <0x00000000 0x100000>;
95 reg = <0x40021000 0x400>;
101 reg = <0x40008140 0x80>;
102 interrupts = <23 0>;
108 reg = <0x40008000 0x20>;
109 interrupts = <14 0>;
117 reg = <0x40008020 0x20>;
118 interrupts = <14 0>;
126 reg = <0x40008040 0x20>;
127 interrupts = <14 0>;
135 reg = <0x40008060 0x20>;
136 interrupts = <14 0>;
144 reg = <0x40008080 0x20>;
145 interrupts = <14 0>;
153 reg = <0x400080A0 0x20>;
154 interrupts = <14 0>;
162 reg = <0x400080C0 0x20>;
163 interrupts = <14 0>;
171 reg = <0x400080E0 0x20>;
172 interrupts = <14 0>;
180 reg = <0x4001c000 0x1000>;
181 interrupts = <15 0>;
185 ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
191 reg = <0x4001d000 0x1000>;
192 interrupts = <16 0>;
196 ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
202 reg = <0x50000100 0x1000>;
204 #size-cells = <0>;
205 interrupts = <4 0>;
207 ambiq,pwrcfg = <&pwrcfg 0x8 0>;
212 reg = <0x50004000 0x1000>;
214 #size-cells = <0>;
215 interrupts = <6 0>;
217 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
222 reg = <0x50005000 0x1000>;
224 #size-cells = <0>;
225 interrupts = <7 0>;
227 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
232 reg = <0x50006000 0x1000>;
234 #size-cells = <0>;
235 interrupts = <8 0>;
237 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
242 reg = <0x50007000 0x1000>;
244 #size-cells = <0>;
245 interrupts = <9 0>;
247 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
252 reg = <0x50008000 0x1000>;
254 #size-cells = <0>;
255 interrupts = <10 0>;
257 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
262 reg = <0x50009000 0x1000>;
264 #size-cells = <0>;
265 interrupts = <11 0>;
267 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
272 reg = <0x50004000 0x1000>;
274 #size-cells = <0>;
275 interrupts = <6 0>;
277 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
282 reg = <0x50005000 0x1000>;
284 #size-cells = <0>;
285 interrupts = <7 0>;
287 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
292 reg = <0x50006000 0x1000>;
294 #size-cells = <0>;
295 interrupts = <8 0>;
297 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
302 reg = <0x50007000 0x1000>;
304 #size-cells = <0>;
305 interrupts = <9 0>;
307 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
312 reg = <0x50008000 0x1000>;
314 #size-cells = <0>;
315 interrupts = <10 0>;
317 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
322 reg = <0x50009000 0x1000>;
324 #size-cells = <0>;
325 interrupts = <11 0>;
327 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
332 reg = <0x50010000 0x400>;
333 interrupts = <18 0>;
339 ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
344 reg = <0x40020000 0x400>;
345 interrupts = <20 0>;
347 #size-cells = <0>;
349 ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
354 reg = <0x40004240 0xD0>;
355 interrupts = <2 0>;
362 reg = <0x5000c000 0x414>;
365 #size-cells = <0>;
367 ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
369 bt_hci_apollo: bt-hci@0 {
372 reg = <0>;
378 reg = <0x40010000 0x800>;
380 #size-cells = <0>;
384 gpio-map-mask = <0xffffffe0 0xffffffc0>;
385 gpio-map-pass-thru = <0x1f 0x3f>;
387 0x00 0x0 &gpio0_31 0x0 0x0
388 0x20 0x0 &gpio32_63 0x0 0x0
390 reg = <0x40010000>;
393 #size-cells = <0>;
396 gpio0_31: gpio0_31@0 {
400 reg = <0>;
401 interrupts = <13 0>;
409 reg = <0x20>;
410 interrupts = <13 0>;
419 reg = <0x40024000 0x400>;
420 interrupts = <1 0>;