1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/adc/adc.h>
7#include <zephyr/dt-bindings/i2c/i2c.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	clocks {
12		uartclk: apb-pclk {
13			compatible = "fixed-clock";
14			clock-frequency = <DT_FREQ_M(24)>;
15			#clock-cells = <0>;
16		};
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			cpu-power-states = <&idle &suspend_to_ram>;
27			#address-cells = <1>;
28			#size-cells = <1>;
29
30			itm: itm@e0000000 {
31				compatible = "arm,armv7m-itm";
32				reg = <0xe0000000 0x1000>;
33				swo-ref-frequency = <DT_FREQ_M(6)>;
34			};
35		};
36
37		power-states {
38			idle: idle {
39				compatible = "zephyr,power-state";
40				power-state-name = "suspend-to-idle";
41				/* As Apollo3blue datasheet, run_to_sleep and sleep_to_run
42				 * transition time are both lower than 1us, but considering
43				 * the software overhead we set a bigger value.
44				 */
45				min-residency-us = <100>;
46				exit-latency-us = <5>;
47			};
48
49			suspend_to_ram: suspend_to_ram {
50				compatible = "zephyr,power-state";
51				power-state-name = "suspend-to-ram";
52				/* As Apollo3blue datasheet, run_to_deepsleep transition time is
53				 * the software overhead 1us and deepsleep_to_run transition time
54				 * is about 25us,but considering the software overhead, we set
55				 * a bigger value.
56				 */
57				min-residency-us = <2000>;
58				exit-latency-us = <125>;
59			};
60		};
61	};
62
63	/* TCM */
64	tcm: tcm@10000000 {
65		compatible = "zephyr,memory-region";
66		reg = <0x10000000 0x10000>;
67		zephyr,memory-region = "ITCM";
68	};
69
70	/* SRAM */
71	sram0: memory@10010000 {
72		compatible = "mmio-sram";
73		reg = <0x10010000 0x50000>;
74	};
75
76	soc {
77		compatible = "ambiq,apollo3-blue", "ambiq,apollo3x", "simple-bus";
78
79		flash: flash-controller@0 {
80			compatible = "ambiq,flash-controller";
81			reg = <0x00000000 0x100000>;
82
83			#address-cells = <1>;
84			#size-cells = <1>;
85
86			/* Flash region */
87			flash0: flash@0 {
88				compatible = "soc-nv-flash";
89				reg = <0x00000000 0x100000>;
90			};
91		};
92
93		pwrcfg: pwrcfg@40021000 {
94			compatible = "ambiq,pwrctrl";
95			reg = <0x40021000 0x400>;
96			#pwrcfg-cells = <2>;
97		};
98
99		stimer0: stimer@40008140 {
100			compatible = "ambiq,stimer";
101			reg = <0x40008140 0x80>;
102			interrupts = <23 0>;
103			status = "okay";
104		};
105
106		counter0: counter@40008000 {
107			compatible = "ambiq,counter";
108			reg = <0x40008000 0x20>;
109			interrupts = <14 0>;
110			clock-frequency = <DT_FREQ_M(3)>;
111			clk-source = <2>;
112			status = "disabled";
113		};
114
115		counter1: counter@40008020 {
116			compatible = "ambiq,counter";
117			reg = <0x40008020 0x20>;
118			interrupts = <14 0>;
119			clock-frequency = <DT_FREQ_M(3)>;
120			clk-source = <2>;
121			status = "disabled";
122		};
123
124		counter2: counter@40008040 {
125			compatible = "ambiq,counter";
126			reg = <0x40008040 0x20>;
127			interrupts = <14 0>;
128			clock-frequency = <DT_FREQ_M(3)>;
129			clk-source = <2>;
130			status = "disabled";
131		};
132
133		counter3: counter@40008060 {
134			compatible = "ambiq,counter";
135			reg = <0x40008060 0x20>;
136			interrupts = <14 0>;
137			clock-frequency = <DT_FREQ_M(3)>;
138			clk-source = <2>;
139			status = "disabled";
140		};
141
142		counter4: counter@40008080 {
143			compatible = "ambiq,counter";
144			reg = <0x40008080 0x20>;
145			interrupts = <14 0>;
146			clock-frequency = <DT_FREQ_M(3)>;
147			clk-source = <2>;
148			status = "disabled";
149		};
150
151		counter5: counter@400080a0 {
152			compatible = "ambiq,counter";
153			reg = <0x400080A0 0x20>;
154			interrupts = <14 0>;
155			clock-frequency = <DT_FREQ_M(3)>;
156			clk-source = <2>;
157			status = "disabled";
158		};
159
160		counter6: counter@400080c0 {
161			compatible = "ambiq,counter";
162			reg = <0x400080C0 0x20>;
163			interrupts = <14 0>;
164			clock-frequency = <DT_FREQ_M(3)>;
165			clk-source = <2>;
166			status = "disabled";
167		};
168
169		counter7: counter@400080e0 {
170			compatible = "ambiq,counter";
171			reg = <0x400080E0 0x20>;
172			interrupts = <14 0>;
173			clock-frequency = <DT_FREQ_M(3)>;
174			clk-source = <2>;
175			status = "disabled";
176		};
177
178		uart0: uart@4001c000 {
179			compatible = "ambiq,uart", "arm,pl011";
180			reg = <0x4001c000 0x1000>;
181			interrupts = <15 0>;
182			interrupt-names = "UART0";
183			status = "disabled";
184			clocks = <&uartclk>;
185			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
186			zephyr,pm-device-runtime-auto;
187		};
188
189		uart1: uart@4001d000 {
190			compatible = "ambiq,uart", "arm,pl011";
191			reg = <0x4001d000 0x1000>;
192			interrupts = <16 0>;
193			interrupt-names = "UART1";
194			status = "disabled";
195			clocks = <&uartclk>;
196			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
197			zephyr,pm-device-runtime-auto;
198		};
199
200		spid0: spi@50000100 {
201			compatible = "ambiq,spid";
202			reg = <0x50000100 0x1000>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			interrupts = <4 0>;
206			status = "disabled";
207			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
208			zephyr,pm-device-runtime-auto;
209		};
210
211		spi0: spi@50004000 {
212			reg = <0x50004000 0x1000>;
213			#address-cells = <1>;
214			#size-cells = <0>;
215			interrupts = <6 0>;
216			status = "disabled";
217			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
218			zephyr,pm-device-runtime-auto;
219		};
220
221		spi1: spi@50005000 {
222			reg = <0x50005000 0x1000>;
223			#address-cells = <1>;
224			#size-cells = <0>;
225			interrupts = <7 0>;
226			status = "disabled";
227			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
228			zephyr,pm-device-runtime-auto;
229		};
230
231		spi2: spi@50006000 {
232			reg = <0x50006000 0x1000>;
233			#address-cells = <1>;
234			#size-cells = <0>;
235			interrupts = <8 0>;
236			status = "disabled";
237			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
238			zephyr,pm-device-runtime-auto;
239		};
240
241		spi3: spi@50007000 {
242			reg = <0x50007000 0x1000>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupts = <9 0>;
246			status = "disabled";
247			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
248			zephyr,pm-device-runtime-auto;
249		};
250
251		spi4: spi@50008000 {
252			reg = <0x50008000 0x1000>;
253			#address-cells = <1>;
254			#size-cells = <0>;
255			interrupts = <10 0>;
256			status = "disabled";
257			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
258			zephyr,pm-device-runtime-auto;
259		};
260
261		spi5: spi@50009000 {
262			reg = <0x50009000 0x1000>;
263			#address-cells = <1>;
264			#size-cells = <0>;
265			interrupts = <11 0>;
266			status = "disabled";
267			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
268			zephyr,pm-device-runtime-auto;
269		};
270
271		i2c0: i2c@50004000 {
272			reg = <0x50004000 0x1000>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275			interrupts = <6 0>;
276			status = "disabled";
277			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
278			zephyr,pm-device-runtime-auto;
279		};
280
281		i2c1: i2c@50005000 {
282			reg = <0x50005000 0x1000>;
283			#address-cells = <1>;
284			#size-cells = <0>;
285			interrupts = <7 0>;
286			status = "disabled";
287			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
288			zephyr,pm-device-runtime-auto;
289		};
290
291		i2c2: i2c@50006000 {
292			reg = <0x50006000 0x1000>;
293			#address-cells = <1>;
294			#size-cells = <0>;
295			interrupts = <8 0>;
296			status = "disabled";
297			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
298			zephyr,pm-device-runtime-auto;
299		};
300
301		i2c3: i2c@50007000 {
302			reg = <0x50007000 0x1000>;
303			#address-cells = <1>;
304			#size-cells = <0>;
305			interrupts = <9 0>;
306			status = "disabled";
307			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
308			zephyr,pm-device-runtime-auto;
309		};
310
311		i2c4: i2c@50008000 {
312			reg = <0x50008000 0x1000>;
313			#address-cells = <1>;
314			#size-cells = <0>;
315			interrupts = <10 0>;
316			status = "disabled";
317			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
318			zephyr,pm-device-runtime-auto;
319		};
320
321		i2c5: i2c@50009000 {
322			reg = <0x50009000 0x1000>;
323			#address-cells = <1>;
324			#size-cells = <0>;
325			interrupts = <11 0>;
326			status = "disabled";
327			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
328			zephyr,pm-device-runtime-auto;
329		};
330
331		adc0: adc@50010000 {
332			reg = <0x50010000 0x400>;
333			interrupts = <18 0>;
334			interrupt-names = "ADC";
335			channel-count = <10>;
336			internal-vref-mv = <1500>;
337			status = "disabled";
338			#io-channel-cells = <1>;
339			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
340		};
341
342		mspi0: spi@40020000 {
343			compatible = "ambiq,mspi";
344			reg = <0x40020000 0x400>;
345			interrupts = <20 0>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			status = "disabled";
349			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
350		};
351
352		rtc0: rtc@40004240 {
353			compatible = "ambiq,rtc";
354			reg = <0x40004240 0xD0>;
355			interrupts = <2 0>;
356			alarms-count = <1>;
357			status = "disabled";
358		};
359
360		bleif: spi@5000c000 {
361			compatible = "ambiq,spi-bleif";
362			reg = <0x5000c000 0x414>;
363			interrupts = <12 1>;
364			#address-cells = <1>;
365			#size-cells = <0>;
366			status = "disabled";
367			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
368
369			bt_hci_apollo: bt-hci@0 {
370				compatible = "ambiq,bt-hci-spi";
371				spi-max-frequency = <DT_FREQ_M(6)>;
372				reg = <0>;
373			};
374		};
375
376		pinctrl: pin-controller@40010000 {
377			compatible = "ambiq,apollo3-pinctrl";
378			reg = <0x40010000 0x800>;
379			#address-cells = <1>;
380			#size-cells = <0>;
381
382			gpio: gpio@40010000 {
383				compatible = "ambiq,gpio";
384				gpio-map-mask = <0xffffffe0 0xffffffc0>;
385				gpio-map-pass-thru = <0x1f 0x3f>;
386				gpio-map = <
387					0x00 0x0 &gpio0_31 0x0 0x0
388					0x20 0x0 &gpio32_63 0x0 0x0
389				>;
390				reg = <0x40010000>;
391				#gpio-cells = <2>;
392				#address-cells = <1>;
393				#size-cells = <0>;
394				ranges;
395
396				gpio0_31: gpio0_31@0 {
397					compatible = "ambiq,gpio-bank";
398					gpio-controller;
399					#gpio-cells = <2>;
400					reg = <0>;
401					interrupts = <13 0>;
402					status = "disabled";
403				};
404
405				gpio32_63: gpio32_63@20 {
406					compatible = "ambiq,gpio-bank";
407					gpio-controller;
408					#gpio-cells = <2>;
409					reg = <0x20>;
410					interrupts = <13 0>;
411					status = "disabled";
412					ngpios = <18>;
413				};
414			};
415		};
416
417		wdt0: watchdog@40024000 {
418			compatible = "ambiq,watchdog";
419			reg = <0x40024000 0x400>;
420			interrupts = <1 0>;
421			clock-frequency = <16>;
422			status = "disabled";
423		};
424	};
425};
426
427&nvic {
428	arm,num-irq-priority-bits = <3>;
429};
430