Lines Matching +full:0 +full:x40024000
24 #size-cells = <0>;
25 reg = <0x40013000 0x400>;
28 dmas = <&dma2 3 3 0x400 0x3
29 &dma2 2 3 0x400 0x3>;
36 reg = <0x40004800 0x400>;
39 interrupts = <39 0>;
45 reg = <0x40004c00 0x400>;
48 interrupts = <52 0>;
54 reg = <0x40005000 0x400>;
57 interrupts = <53 0>;
63 reg = <0x40006400 0x400>;
64 interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
72 reg = <0x40006800 0x400>;
73 interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
77 master-can-reg = <0x40006400>;
84 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
89 reg = <0x40040000 0x40000>;
90 interrupts = <77 0>, <74 0>, <75 0>;
97 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
103 reg = <0x40024000 DT_SIZE_K(4)>;
111 reg = <0x40012100 0x050>;
113 interrupts = <18 0>;
116 resolutions = <STM32_ADC_RES(12, 0x00)
117 STM32_ADC_RES(10, 0x01)
118 STM32_ADC_RES(8, 0x02)
119 STM32_ADC_RES(6, 0x03)>;
128 reg = <0x40012200 0x050>;
130 interrupts = <18 0>;
133 resolutions = <STM32_ADC_RES(12, 0x00)
134 STM32_ADC_RES(10, 0x01)
135 STM32_ADC_RES(8, 0x02)
136 STM32_ADC_RES(6, 0x03)>;
145 reg = <0x40007400 0x400>;
153 reg = <0xa0000000 0x400>;
154 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
160 #size-cells = <0>;
172 #phy-cells = <0>;