1/*
2 * Copyright (c) 2018 Philémon Jaermann
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f401.dtsi>
8#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
10
11/ {
12	clocks {
13		plli2s: plli2s {
14			compatible = "st,stm32f411-plli2s-clock";
15		};
16	};
17
18	soc {
19		compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
20
21		i2s1: i2s@40013000 {
22			compatible = "st,stm32-i2s";
23			#address-cells = <1>;
24			#size-cells = <0>;
25			reg = <0x40013000 0x400>;
26			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
27			interrupts = <35 5>;
28			dmas = <&dma2 3 3 0x400 0x3
29				&dma2 2 3 0x400 0x3>;
30			dma-names = "tx", "rx";
31			status = "disabled";
32		};
33
34		usart3: serial@40004800 {
35			compatible = "st,stm32-usart", "st,stm32-uart";
36			reg = <0x40004800 0x400>;
37			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
38			resets = <&rctl STM32_RESET(APB1, 18U)>;
39			interrupts = <39 0>;
40			status = "disabled";
41		};
42
43		uart4: serial@40004c00 {
44			compatible ="st,stm32-uart";
45			reg = <0x40004c00 0x400>;
46			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
47			resets = <&rctl STM32_RESET(APB1, 19U)>;
48			interrupts = <52 0>;
49			status = "disabled";
50		};
51
52		uart5: serial@40005000 {
53			compatible = "st,stm32-uart";
54			reg = <0x40005000 0x400>;
55			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
56			resets = <&rctl STM32_RESET(APB1, 20U)>;
57			interrupts = <53 0>;
58			status = "disabled";
59		};
60
61		can1: can@40006400 {
62			compatible = "st,stm32-bxcan";
63			reg = <0x40006400 0x400>;
64			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
65			interrupt-names = "TX", "RX0", "RX1", "SCE";
66			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
67			status = "disabled";
68		};
69
70		can2: can@40006800 {
71			compatible = "st,stm32-bxcan";
72			reg = <0x40006800 0x400>;
73			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
74			interrupt-names = "TX", "RX0", "RX1", "SCE";
75			/* also enabling clock for can1 (master instance) */
76			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
77			master-can-reg = <0x40006400>;
78			status = "disabled";
79		};
80
81		usbotg_fs: usb@50000000 {
82			num-bidir-endpoints = <6>;
83			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
84				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
85		};
86
87		usbotg_hs: usb@40040000 {
88			compatible = "st,stm32-otghs";
89			reg = <0x40040000 0x40000>;
90			interrupts = <77 0>, <74 0>, <75 0>;
91			interrupt-names = "otghs", "ep1_out", "ep1_in";
92			num-bidir-endpoints = <9>;
93			ram-size = <4096>;
94			maximum-speed = "full-speed";
95			phys = <&otghs_fs_phy>;
96			clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
97				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
98			status = "disabled";
99		};
100
101		backup_sram: memory@40024000 {
102			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
103			reg = <0x40024000 DT_SIZE_K(4)>;
104			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
105			zephyr,memory-region = "BACKUP_SRAM";
106			status = "disabled";
107		};
108
109		adc2: adc@40012100 {
110			compatible = "st,stm32-adc";
111			reg = <0x40012100 0x050>;
112			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
113			interrupts = <18 0>;
114			status = "disabled";
115			#io-channel-cells = <1>;
116			resolutions = <STM32_ADC_RES(12, 0x00)
117				       STM32_ADC_RES(10, 0x01)
118				       STM32_ADC_RES(8, 0x02)
119				       STM32_ADC_RES(6, 0x03)>;
120			sampling-times = <3 15 28 56 84 112 144 480>;
121			st,adc-clock-source = "SYNC";
122			st,adc-sequencer = "FULLY_CONFIGURABLE";
123			st,adc-oversampler = "OVERSAMPLER_NONE";
124		};
125
126		adc3: adc@40012200 {
127			compatible = "st,stm32-adc";
128			reg = <0x40012200 0x050>;
129			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
130			interrupts = <18 0>;
131			status = "disabled";
132			#io-channel-cells = <1>;
133			resolutions = <STM32_ADC_RES(12, 0x00)
134				       STM32_ADC_RES(10, 0x01)
135				       STM32_ADC_RES(8, 0x02)
136				       STM32_ADC_RES(6, 0x03)>;
137			sampling-times = <3 15 28 56 84 112 144 480>;
138			st,adc-clock-source = "SYNC";
139			st,adc-sequencer = "FULLY_CONFIGURABLE";
140			st,adc-oversampler = "OVERSAMPLER_NONE";
141		};
142
143		dac1: dac@40007400 {
144			compatible = "st,stm32-dac";
145			reg = <0x40007400 0x400>;
146			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
147			status = "disabled";
148			#io-channel-cells = <1>;
149		};
150
151		fmc: memory-controller@a0000000 {
152			compatible = "st,stm32-fmc";
153			reg = <0xa0000000 0x400>;
154			clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
155			status = "disabled";
156
157			sdram: sdram {
158				compatible = "st,stm32-fmc-sdram";
159				#address-cells = <1>;
160				#size-cells = <0>;
161				status = "disabled";
162			};
163		};
164	};
165
166	die_temp: dietemp {
167		io-channels = <&adc1 18>;
168	};
169
170	otghs_fs_phy: otghs_fs_phy {
171		compatible = "usb-nop-xceiv";
172		#phy-cells = <0>;
173	};
174};
175