Lines Matching +full:0 +full:x40024000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0>;
34 * across the 0x2000_0000 boundary are not supported in the Arm
43 reg = <0x1fff0000 DT_SIZE_K(64)>;
49 reg = <0x20000000 DT_SIZE_K(192)>;
85 reg = <0x4000d000 0x824>;
92 reg = <0x40064000 0xd>;
98 reg = <0x40065000 0x4>;
105 reg = <0x4003d000 0x1000>;
106 interrupts = <46 0>, <47 0>;
114 reg = <0x40047000 0x1060>;
121 #clock-cells = <0>;
128 #clock-cells = <0>;
135 #clock-cells = <0>;
142 #clock-cells = <0>;
148 reg = <0x40020000 0x18>;
149 interrupts = <18 0>, <19 0>;
156 flash0: flash@0 {
158 reg = <0 DT_SIZE_M(1)>;
168 #size-cells = <0>;
169 reg = <0x40066000 0x1000>;
170 interrupts = <24 0>;
171 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
179 #size-cells = <0>;
180 reg = <0x40067000 0x1000>;
181 interrupts = <25 0>;
182 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
190 #size-cells = <0>;
191 reg = <0x400e6000 0x1000>;
192 interrupts = <74 0>;
193 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
199 reg = <0x4006a000 0x1000>;
200 interrupts = <31 0>, <32 0>;
202 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
209 reg = <0x4006b000 0x1000>;
210 interrupts = <33 0>, <34 0>;
212 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
219 reg = <0x4006c000 0x1000>;
220 interrupts = <35 0>, <36 0>;
222 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
229 reg = <0x4006d000 0x1000>;
230 interrupts = <37 0>, <38 0>;
232 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
239 reg = <0x400ea000 0x1000>;
240 interrupts = <66 0>, <67 0>;
242 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
249 reg = <0x400eb000 0x1000>;
250 interrupts = <68 0>, <69 0>;
252 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
259 reg = <0x40049000 0xd0>;
260 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
265 reg = <0x4004a000 0xd0>;
266 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
271 reg = <0x4004b000 0xd0>;
272 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
277 reg = <0x4004c000 0xd0>;
278 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
283 reg = <0x4004d000 0xd0>;
284 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
290 reg = <0x400ff000 0x40>;
300 reg = <0x400ff040 0x40>;
310 reg = <0x400ff080 0x40>;
320 reg = <0x400ff0c0 0x40>;
330 reg = <0x400ff100 0x40>;
339 reg = <0x4002c000 0x88>;
341 dmas = <&edma0 0 14>, <&edma0 0 15>;
345 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
347 #size-cells = <0>;
353 reg = <0x4002d000 0x88>;
355 dmas = <&edma0 0 16>, <&edma0 0 16>;
360 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
362 #size-cells = <0>;
368 reg = <0x400ac000 0x88>;
370 dmas = <&edma0 0 38>, <&edma0 0 39>;
375 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
377 #size-cells = <0>;
383 reg = <0x40052000 16>;
384 interrupts = <22 0>;
385 clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
390 reg = <0x40038000 0x98>;
391 interrupts = <42 0>;
399 reg = <0x40039000 0x98>;
400 interrupts = <43 0>;
408 reg = <0x4003a000 0x98>;
409 interrupts = <44 0>;
417 reg = <0x400b9000 0x98>;
418 interrupts = <71 0>;
426 reg = <0x4003b000 0x70>;
427 clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
428 <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
429 dmas = <&edma0 0 40>;
431 clk-source = <0>;
432 interrupts = <39 0>;
439 reg = <0x400bb000 0x70>;
440 clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
441 <&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
442 dmas = <&edma0 0 41>;
444 clk-source = <0>;
445 interrupts = <73 0>;
452 reg = <0x400cc000 0x1000>;
453 interrupts = <56 0>;
461 reg = <0x400cd000 0x1000>;
462 interrupts = <72 0>;
470 reg = <0x40072000 0x1000>;
479 reg = <0x400c0000 0x620>;
480 clocks = <&sim KINETIS_SIM_ENET_CLK 0 0>;
483 interrupts = <83 0>, <84 0>, <85 0>;
494 #size-cells = <0>;
498 interrupts = <82 0>;
500 clocks = <&sim KINETIS_SIM_ENET_1588_CLK 0 0>;
507 reg = <0x40029000 0x1000>;
509 interrupts = <23 0>;
514 reg = <0x40024000 0x1000>;
515 interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
516 interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
517 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
529 reg = <0x40008000 0x1000>,
530 <0x40021000 0x1000>;
531 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
532 <4 0>, <5 0>, <6 0>, <7 0>,
533 <8 0>, <9 0>, <10 0>, <11 0>,
534 <12 0>, <13 0>, <14 0>, <15 0>,
535 <16 0>;
536 clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
537 <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
543 reg = <0x40037000 0x1000>;
544 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
546 max-load-value = <0xffffffff>;
548 #size-cells = <0>;
550 pit0_channel0: pit0_channel@0 {
552 reg = <0>;
553 interrupts = <48 0>;
560 interrupts = <49 0>;
567 interrupts = <50 0>;
574 interrupts = <51 0>;