1/* 2 * Copyright (c) 2024 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <mem.h> 9#include <freq.h> 10#include <zephyr/dt-bindings/clock/numaker_m2l31x_clock.h> 11#include <zephyr/dt-bindings/reset/numaker_m2l31x_reset.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/adc/adc.h> 15 16/ { 17 chosen { 18 zephyr,flash-controller = &rmc; 19 }; 20 21 aliases { 22 rtc = &rtc; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-m23"; 32 reg = <0>; 33 }; 34 }; 35 36 sysclk: system-clock { 37 compatible = "fixed-clock"; 38 clock-frequency = <DT_FREQ_M(72)>; 39 #clock-cells = <0>; 40 }; 41 42 soc { 43 scc: system-clock-controller@40000200 { 44 compatible = "nuvoton,numaker-scc"; 45 reg = <0x40000200 0x100>; 46 #clock-cells = <0>; 47 lxt = "enable"; 48 hirc48m = "enable"; 49 clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | 50 NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; 51 core-clock = <DT_FREQ_M(72)>; 52 powerdown-mode = <NUMAKER_CLK_PMUCTL_PDMSEL_DPD0>; 53 54 pcc: peripheral-clock-controller { 55 compatible = "nuvoton,numaker-pcc"; 56 #clock-cells = <3>; 57 }; 58 }; 59 60 rst: reset-controller@40000000 { 61 compatible = "nuvoton,numaker-rst"; 62 reg = <0x40000000 0x20>; 63 #reset-cells = <1>; 64 }; 65 66 rmc: flash-controller@4000c000 { 67 compatible = "nuvoton,numaker-rmc"; 68 reg = <0x4000c000 0x1000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 72 flash0: flash@0 { 73 compatible = "soc-nv-flash"; 74 erase-block-size = <4096>; 75 write-block-size = <4>; 76 }; 77 }; 78 79 uart0: serial@40070000 { 80 compatible = "nuvoton,numaker-uart"; 81 reg = <0x40070000 0x1000>; 82 interrupts = <36 0>; 83 resets = <&rst NUMAKER_UART0_RST>; 84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC 85 NUMAKER_CLK_CLKDIV0_UART0(1)>; 86 status = "disabled"; 87 }; 88 89 uart1: serial@40071000 { 90 compatible = "nuvoton,numaker-uart"; 91 reg = <0x40071000 0x1000>; 92 interrupts = <37 0>; 93 resets = <&rst NUMAKER_UART1_RST>; 94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC 95 NUMAKER_CLK_CLKDIV0_UART1(1)>; 96 status = "disabled"; 97 }; 98 99 uart2: serial@40072000 { 100 compatible = "nuvoton,numaker-uart"; 101 reg = <0x40072000 0x1000>; 102 interrupts = <48 0>; 103 resets = <&rst NUMAKER_UART2_RST>; 104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC 105 NUMAKER_CLK_CLKDIV4_UART2(1)>; 106 status = "disabled"; 107 }; 108 109 uart3: serial@40073000 { 110 compatible = "nuvoton,numaker-uart"; 111 reg = <0x40073000 0x1000>; 112 interrupts = <49 0>; 113 resets = <&rst NUMAKER_UART3_RST>; 114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC 115 NUMAKER_CLK_CLKDIV4_UART3(1)>; 116 status = "disabled"; 117 }; 118 119 uart4: serial@40074000 { 120 compatible = "nuvoton,numaker-uart"; 121 reg = <0x40074000 0x1000>; 122 interrupts = <74 0>; 123 resets = <&rst NUMAKER_UART4_RST>; 124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC 125 NUMAKER_CLK_CLKDIV4_UART4(1)>; 126 status = "disabled"; 127 }; 128 129 uart5: serial@40075000 { 130 compatible = "nuvoton,numaker-uart"; 131 reg = <0x40075000 0x1000>; 132 interrupts = <75 0>; 133 resets = <&rst NUMAKER_UART5_RST>; 134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC 135 NUMAKER_CLK_CLKDIV4_UART5(1)>; 136 status = "disabled"; 137 }; 138 139 uart6: serial@40076000 { 140 compatible = "nuvoton,numaker-uart"; 141 reg = <0x40076000 0x1000>; 142 interrupts = <102 0>; 143 resets = <&rst NUMAKER_UART6_RST>; 144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC 145 NUMAKER_CLK_CLKDIV4_UART6(1)>; 146 status = "disabled"; 147 }; 148 149 uart7: serial@40077000 { 150 compatible = "nuvoton,numaker-uart"; 151 reg = <0x40077000 0x1000>; 152 interrupts = <103 0>; 153 resets = <&rst NUMAKER_UART7_RST>; 154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC 155 NUMAKER_CLK_CLKDIV4_UART7(1)>; 156 status = "disabled"; 157 }; 158 159 pinctrl: pin-controller@40000080 { 160 compatible = "nuvoton,numaker-pinctrl"; 161 reg = <0x40000080 0x20 162 0x40000500 0x80>; 163 reg-names = "mfos", "mfp"; 164 }; 165 166 gpioa: gpio@40004000 { 167 compatible = "nuvoton,numaker-gpio"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 reg = <0x40004000 0x40>; 171 clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; 172 status = "disabled"; 173 interrupts = <16 2>; 174 }; 175 176 gpiob: gpio@40004040 { 177 compatible = "nuvoton,numaker-gpio"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 reg = <0x40004040 0x40>; 181 clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; 182 status = "disabled"; 183 interrupts = <17 2>; 184 }; 185 186 gpioc: gpio@40004080 { 187 compatible = "nuvoton,numaker-gpio"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 reg = <0x40004080 0x40>; 191 clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; 192 status = "disabled"; 193 interrupts = <18 2>; 194 }; 195 196 gpiod: gpio@400040c0 { 197 compatible = "nuvoton,numaker-gpio"; 198 gpio-controller; 199 #gpio-cells = <2>; 200 reg = <0x400040c0 0x40>; 201 clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; 202 status = "disabled"; 203 interrupts = <19 2>; 204 }; 205 206 gpioe: gpio@40004100 { 207 compatible = "nuvoton,numaker-gpio"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 reg = <0x40004100 0x40>; 211 clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; 212 status = "disabled"; 213 interrupts = <20 2>; 214 }; 215 216 gpiof: gpio@40004140 { 217 compatible = "nuvoton,numaker-gpio"; 218 gpio-controller; 219 #gpio-cells = <2>; 220 reg = <0x40004140 0x40>; 221 clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; 222 status = "disabled"; 223 interrupts = <21 2>; 224 }; 225 226 spi0: spi@40061000 { 227 compatible = "nuvoton,numaker-spi"; 228 reg = <0x40061000 0x6c>; 229 interrupts = <23 0>; 230 resets = <&rst NUMAKER_SPI0_RST>; 231 clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 status = "disabled"; 235 }; 236 237 spi1: spi@40062000 { 238 compatible = "nuvoton,numaker-spi"; 239 reg = <0x40062000 0x6c>; 240 interrupts = <51 0>; 241 resets = <&rst NUMAKER_SPI1_RST>; 242 clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 status = "disabled"; 246 }; 247 248 spi2: spi@40063000 { 249 compatible = "nuvoton,numaker-spi"; 250 reg = <0x40063000 0x6c>; 251 interrupts = <52 0>; 252 resets = <&rst NUMAKER_SPI2_RST>; 253 clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 status = "disabled"; 257 }; 258 259 spi3: spi@40064000 { 260 compatible = "nuvoton,numaker-spi"; 261 reg = <0x40064000 0x6c>; 262 interrupts = <62 0>; 263 resets = <&rst NUMAKER_SPI3_RST>; 264 clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 status = "disabled"; 268 }; 269 270 i2c0: i2c@40080000 { 271 compatible = "nuvoton,numaker-i2c"; 272 clock-frequency = <I2C_BITRATE_STANDARD>; 273 reg = <0x40080000 0x1000>; 274 interrupts = <38 0>; 275 resets = <&rst NUMAKER_I2C0_RST>; 276 clocks = <&pcc NUMAKER_I2C0_MODULE 0 0>; 277 status = "disabled"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 }; 281 282 i2c1: i2c@40081000 { 283 compatible = "nuvoton,numaker-i2c"; 284 clock-frequency = <I2C_BITRATE_STANDARD>; 285 reg = <0x40081000 0x1000>; 286 interrupts = <39 0>; 287 resets = <&rst NUMAKER_I2C1_RST>; 288 clocks = <&pcc NUMAKER_I2C1_MODULE 0 0>; 289 status = "disabled"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 }; 293 294 i2c2: i2c@40082000 { 295 compatible = "nuvoton,numaker-i2c"; 296 clock-frequency = <I2C_BITRATE_STANDARD>; 297 reg = <0x40082000 0x1000>; 298 interrupts = <82 0>; 299 resets = <&rst NUMAKER_I2C2_RST>; 300 clocks = <&pcc NUMAKER_I2C2_MODULE 0 0>; 301 status = "disabled"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 }; 305 306 i2c3: i2c@40083000 { 307 compatible = "nuvoton,numaker-i2c"; 308 clock-frequency = <I2C_BITRATE_STANDARD>; 309 reg = <0x40083000 0x1000>; 310 interrupts = <83 0>; 311 resets = <&rst NUMAKER_I2C3_RST>; 312 clocks = <&pcc NUMAKER_I2C3_MODULE 0 0>; 313 status = "disabled"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 318 eadc0: eadc@40043000 { 319 compatible = "nuvoton,numaker-adc"; 320 reg = <0x40043000 0xffc>; 321 interrupts = <42 0>; 322 resets = <&rst NUMAKER_EADC0_RST>; 323 clocks = <&pcc NUMAKER_EADC0_MODULE 324 NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 325 NUMAKER_CLK_CLKDIV0_EADC0(2)>; 326 channels = <31>; 327 status = "disabled"; 328 #io-channel-cells = <1>; 329 }; 330 331 rtc: rtc@40041000 { 332 compatible = "nuvoton,numaker-rtc"; 333 reg = <0x40041000 0x138>; 334 interrupts = <6 0>; 335 oscillator = "lxt"; 336 clocks = <&pcc NUMAKER_RTC_MODULE 0 0>; 337 alarms-count = <1>; 338 }; 339 340 epwm0: epwm@40058000 { 341 compatible = "nuvoton,numaker-pwm"; 342 reg = <0x40058000 0x37c>; 343 interrupts = <25 0>, <26 0>, <27 0>; 344 interrupt-names = "pair0", "pair1", "pair2"; 345 resets = <&rst NUMAKER_EPWM0_RST>; 346 prescaler = <19>; 347 clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>; 348 #pwm-cells = <3>; 349 status = "disabled"; 350 }; 351 352 epwm1: epwm@40059000 { 353 compatible = "nuvoton,numaker-pwm"; 354 reg = <0x40059000 0x37c>; 355 interrupts = <29 0>, <30 0>, <31 0>; 356 interrupt-names = "pair0", "pair1", "pair2"; 357 resets = <&rst NUMAKER_EPWM1_RST>; 358 prescaler = <19>; 359 clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>; 360 #pwm-cells = <3>; 361 status = "disabled"; 362 }; 363 364 canfd0: canfd@40020000 { 365 compatible = "nuvoton,numaker-canfd"; 366 reg = <0x40020000 0x200>, <0x40020200 0x1800>; 367 reg-names = "m_can", "message_ram"; 368 interrupts = <112 0>, <113 0>; 369 interrupt-names = "int0", "int1"; 370 resets = <&rst NUMAKER_CANFD0_RST>; 371 clocks = <&pcc NUMAKER_CANFD0_MODULE 372 NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 373 NUMAKER_CLK_CLKDIV5_CANFD0(1)>; 374 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 375 status = "disabled"; 376 }; 377 378 canfd1: canfd@40024000 { 379 compatible = "nuvoton,numaker-canfd"; 380 reg = <0x40024000 0x200>, <0x40024200 0x1800>; 381 reg-names = "m_can", "message_ram"; 382 interrupts = <114 0>, <115 0>; 383 interrupt-names = "int0", "int1"; 384 resets = <&rst NUMAKER_CANFD1_RST>; 385 clocks = <&pcc NUMAKER_CANFD1_MODULE 386 NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 387 NUMAKER_CLK_CLKDIV5_CANFD1(1)>; 388 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 389 status = "disabled"; 390 }; 391 392 usbd: usbd@400c0000 { 393 compatible = "nuvoton,numaker-usbd"; 394 reg = <0x400c0000 0x1000>; 395 interrupts = <53 0>; 396 resets = <&rst NUMAKER_USBD_RST>; 397 clocks = <&pcc NUMAKER_USBD_MODULE NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M 398 NUMAKER_CLK_CLKDIV0_USB(1)>; 399 dma-buffer-size = <1024>; 400 status = "disabled"; 401 num-bidir-endpoints = <19>; 402 disallow-iso-in-out-same-number; 403 }; 404 405 wwdt: watchdog@40096000 { 406 compatible = "nuvoton,numaker-wwdt"; 407 reg = <0x40096000 0x10>; 408 interrupts = <9 0>; 409 clocks = <&pcc NUMAKER_WWDT_MODULE NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0>; 410 status = "disabled"; 411 }; 412 413 tcpc0: utcpd@400c6000 { 414 compatible = "nuvoton,numaker-tcpc"; 415 reg = <0x400c6000 0x1000>, 416 <0x40043000 0x1000>, 417 <0x40050000 0x1000>; 418 reg-names = "utcpd", "eadc", "timer"; 419 interrupts = <108 0>; 420 interrupt-names = "utcpd"; 421 resets = <&rst NUMAKER_UTCPD0_RST>, 422 <&rst NUMAKER_TMR0_RST>; 423 reset-names = "utcpd", "timer"; 424 clocks = <&pcc NUMAKER_UTCPD0_MODULE 0 0>, 425 <&pcc NUMAKER_TMR0_MODULE NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC 0>; 426 clock-names = "utcpd", "timer"; 427 status = "disabled"; 428 429 vbus0: vbus0 { 430 compatible = "nuvoton,numaker-vbus"; 431 status = "disabled"; 432 }; 433 434 ppc0: ppc0 { 435 compatible = "nuvoton,numaker-ppc"; 436 status = "disabled"; 437 }; 438 }; 439 }; 440}; 441 442&nvic { 443 arm,num-irq-priority-bits = <2>; 444}; 445
