Lines Matching +full:0 +full:x40024000
19 reg = <0x40020000 0x2400>;
25 reg = <0x40021400 0x400>;
33 reg = <0x40021800 0x400>;
41 reg = <0x40022000 0x400>;
48 reg = <0x40004800 0x400>;
51 interrupts = <39 0>;
57 reg = <0x40004c00 0x400>;
60 interrupts = <52 0>;
66 reg = <0x40005000 0x400>;
69 interrupts = <53 0>;
75 reg = <0x40001000 0x400>;
78 interrupts = <54 0>;
80 st,prescaler = <0>;
91 reg = <0x40001400 0x400>;
94 interrupts = <55 0>;
96 st,prescaler = <0>;
107 reg = <0x40010400 0x400>;
110 interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
112 st,prescaler = <0>;
130 reg = <0x40001800 0x400>;
133 interrupts = <43 0>;
135 st,prescaler = <0>;
152 reg = <0x40001c00 0x400>;
155 interrupts = <44 0>;
157 st,prescaler = <0>;
174 reg = <0x40002000 0x400>;
177 interrupts = <45 0>;
179 st,prescaler = <0>;
196 reg = <0x40040000 0x40000>;
197 interrupts = <77 0>, <74 0>, <75 0>;
210 reg = <0x40006400 0x400>;
211 interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
219 reg = <0x40006800 0x400>;
220 interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
224 master-can-reg = <0x40006400>;
230 reg = <0x50060800 0x400>;
231 interrupts = <80 0>;
238 reg = <0x40024000 DT_SIZE_K(4)>;
246 reg = <0x40012100 0x050>;
248 interrupts = <18 0>;
251 resolutions = <STM32_ADC_RES(12, 0x00)
252 STM32_ADC_RES(10, 0x01)
253 STM32_ADC_RES(8, 0x02)
254 STM32_ADC_RES(6, 0x03)>;
263 reg = <0x40012200 0x050>;
265 interrupts = <18 0>;
268 resolutions = <STM32_ADC_RES(12, 0x00)
269 STM32_ADC_RES(10, 0x01)
270 STM32_ADC_RES(8, 0x02)
271 STM32_ADC_RES(6, 0x03)>;
280 reg = <0x40007400 0x400>;
289 #phy-cells = <0>;