1/*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/i2c/i2c.h>
10
11/ {
12	aliases {
13		watchdog0 = &wdog;
14	};
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			reg = <0>;
23		};
24	};
25
26	/* Dummy pinctrl node, filled with pin mux options at board level */
27	pinctrl: pinctrl {
28		compatible = "nxp,port-pinctrl";
29		status = "okay";
30	};
31
32	soc {
33		interrupt-parent = <&nvic>;
34
35		mpu: mpu@4000d000 {
36			compatible = "nxp,sysmpu";
37			reg = <0x4000d000 0x1000>;
38			status = "disabled";
39		};
40
41		ftfc: flash-controller@40020000 {
42			compatible = "nxp,kinetis-ftfc";
43			reg = <0x40020000 0x1000>;
44			interrupts = <18 0>, <19 0>, <21 0>;
45			interrupt-names = "command-complete", "read-collision", "double-bit";
46			#address-cells = <1>;
47			#size-cells = <1>;
48			status = "disabled";
49		};
50
51		flexcan0: can@40024000 {
52			compatible = "nxp,flexcan-fd", "nxp,flexcan";
53			reg = <0x40024000 0x1000>;
54			clocks = <&clock NXP_S32_FLEXCAN0_CLK>;
55			clk-source = <1>;
56			status = "disabled";
57		};
58
59		flexcan1: can@40025000 {
60			compatible = "nxp,flexcan-fd", "nxp,flexcan";
61			reg = <0x40025000 0x1000>;
62			clk-source = <1>;
63			status = "disabled";
64		};
65
66		flexcan2: can@4002b000 {
67			compatible = "nxp,flexcan-fd", "nxp,flexcan";
68			reg = <0x4002b000 0x1000>;
69			clk-source = <1>;
70			status = "disabled";
71		};
72
73		lpspi0: spi@4002c000 {
74			compatible = "nxp,lpspi";
75			reg = <0x4002c000 0x1000>;
76			interrupts = <26 0>;
77			clocks = <&clock NXP_S32_LPSPI0_CLK>;
78			#address-cells = <1>;
79			#size-cells = <0>;
80			status = "disabled";
81		};
82
83		lpspi1: spi@4002d000 {
84			compatible = "nxp,lpspi";
85			reg = <0x4002d000 0x1000>;
86			interrupts = <27 0>;
87			#address-cells = <1>;
88			#size-cells = <0>;
89			status = "disabled";
90		};
91
92		lpspi2: spi@4002e000 {
93			compatible = "nxp,lpspi";
94			reg = <0x4002e000 0x1000>;
95			interrupts = <28 0>;
96			#address-cells = <1>;
97			#size-cells = <0>;
98			status = "disabled";
99		};
100
101		porta: pinmux@40049000 {
102			compatible = "nxp,port-pinmux";
103			reg = <0x40049000 0x1000>;
104			clocks = <&clock NXP_S32_PORTA_CLK>;
105		};
106
107		portb: pinmux@4004a000 {
108			compatible = "nxp,port-pinmux";
109			reg = <0x4004a000 0x1000>;
110			clocks = <&clock NXP_S32_PORTB_CLK>;
111		};
112
113		portc: pinmux@4004b000 {
114			compatible = "nxp,port-pinmux";
115			reg = <0x4004b000 0x1000>;
116			clocks = <&clock NXP_S32_PORTC_CLK>;
117		};
118
119		portd: pinmux@4004c000 {
120			compatible = "nxp,port-pinmux";
121			reg = <0x4004c000 0x1000>;
122			clocks = <&clock NXP_S32_PORTD_CLK>;
123		};
124
125		porte: pinmux@4004d000 {
126			compatible = "nxp,port-pinmux";
127			reg = <0x4004d000 0x1000>;
128			clocks = <&clock NXP_S32_PORTE_CLK>;
129		};
130
131		wdog: watchdog@40052000 {
132			compatible = "nxp,wdog32";
133			reg = <0x40052000 0x1000>;
134			interrupts = <22 0>;
135			clocks = <&clock NXP_S32_LPO_128K_CLK>;
136			clk-source = <1>;
137			clk-divider = <256>;
138		};
139
140		clock: clock-controller@40064000 {
141			compatible = "nxp,s32-clock";
142			reg = <0x40064000 0x1000>, <0x40065000 0x1000>;
143			#clock-cells = <1>;
144			status = "okay";
145		};
146
147		lpi2c0: i2c@40066000 {
148			compatible = "nxp,lpi2c";
149			clock-frequency = <I2C_BITRATE_STANDARD>;
150			#address-cells = <1>;
151			#size-cells = <0>;
152			reg = <0x40066000 0x1000>;
153			interrupts = <24 0>;
154			clocks = <&clock NXP_S32_LPI2C0_CLK>;
155			status = "disabled";
156		};
157
158		lpi2c1: i2c@40067000 {
159			compatible = "nxp,lpi2c";
160			clock-frequency = <I2C_BITRATE_STANDARD>;
161			#address-cells = <1>;
162			#size-cells = <0>;
163			reg = <0x40067000 0x1000>;
164			interrupts = <25 0>;
165			status = "disabled";
166		};
167
168		lpuart0: uart@4006a000 {
169			compatible = "nxp,lpuart";
170			reg = <0x4006a000 0x1000>;
171			interrupts = <31 0>;
172			clocks = <&clock NXP_S32_LPUART0_CLK>;
173			status = "disabled";
174		};
175
176		lpuart1: uart@4006b000 {
177			compatible = "nxp,lpuart";
178			reg = <0x4006b000 0x1000>;
179			interrupts = <33 0>;
180			clocks = <&clock NXP_S32_LPUART1_CLK>;
181			status = "disabled";
182		};
183
184		lpuart2: uart@4006c000 {
185			compatible = "nxp,lpuart";
186			reg = <0x4006c000 0x1000>;
187			interrupts = <35 0>;
188			status = "disabled";
189		};
190
191		gpioa: gpio@400ff000 {
192			compatible = "nxp,kinetis-gpio";
193			reg = <0x400ff000 0x40>;
194			interrupts = <59 2>;
195			gpio-controller;
196			#gpio-cells = <2>;
197			nxp,kinetis-port = <&porta>;
198			status = "disabled";
199		};
200
201		gpiob: gpio@400ff040 {
202			compatible = "nxp,kinetis-gpio";
203			reg = <0x400ff040 0x40>;
204			interrupts = <60 2>;
205			gpio-controller;
206			#gpio-cells = <2>;
207			nxp,kinetis-port = <&portb>;
208			status = "disabled";
209		};
210
211		gpioc: gpio@400ff080 {
212			compatible = "nxp,kinetis-gpio";
213			reg = <0x400ff080 0x40>;
214			interrupts = <61 2>;
215			gpio-controller;
216			#gpio-cells = <2>;
217			nxp,kinetis-port = <&portc>;
218			status = "disabled";
219		};
220
221		gpiod: gpio@400ff0c0 {
222			compatible = "nxp,kinetis-gpio";
223			reg = <0x400ff0c0 0x40>;
224			interrupts = <62 2>;
225			gpio-controller;
226			#gpio-cells = <2>;
227			nxp,kinetis-port = <&portd>;
228			status = "disabled";
229		};
230
231		gpioe: gpio@400ff100 {
232			compatible = "nxp,kinetis-gpio";
233			reg = <0x400ff100 0x40>;
234			interrupts = <63 2>;
235			gpio-controller;
236			#gpio-cells = <2>;
237			nxp,kinetis-port = <&porte>;
238			status = "disabled";
239		};
240
241		ftm0: ftm@40038000 {
242			compatible = "nxp,ftm";
243			reg = <0x40038000 0x1000>;
244			interrupts = <99 0>, <100 0>, <101 0>, <102 0>, <104 0>;
245			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
246			clocks = <&clock NXP_S32_CORE_CLK>;
247			prescaler = <1>;
248			status = "disabled";
249		};
250
251		ftm1: ftm@40039000 {
252			compatible = "nxp,ftm";
253			reg = <0x40039000 0x1000>;
254			interrupts = <105 0>, <106 0>, <107 0>, <108 0>, <110 0>;
255			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
256			clocks = <&clock NXP_S32_CORE_CLK>;
257			prescaler = <1>;
258			status = "disabled";
259		};
260
261		ftm2: ftm@4003a000 {
262			compatible = "nxp,ftm";
263			reg = <0x4003a000 0x1000>;
264			interrupts = <111 0>, <112 0>, <113 0>, <114 0>, <116 0>;
265			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
266			clocks = <&clock NXP_S32_CORE_CLK>;
267			prescaler = <1>;
268			status = "disabled";
269		};
270
271		ftm3: ftm@40026000 {
272			compatible = "nxp,ftm";
273			reg = <0x40026000 0x1000>;
274			interrupts = <117 0>, <118 0>, <119 0>, <120 0>, <122 0>;
275			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
276			clocks = <&clock NXP_S32_CORE_CLK>;
277			prescaler = <1>;
278			status = "disabled";
279		};
280
281		ftm4: ftm@4006e000 {
282			compatible = "nxp,ftm";
283			reg = <0x4006e000 0x1000>;
284			interrupts = <123 0>, <124 0>, <125 0>, <126 0>, <128 0>;
285			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
286			clocks = <&clock NXP_S32_CORE_CLK>;
287			prescaler = <1>;
288			status = "disabled";
289		};
290
291		ftm5: ftm@4006f000 {
292			compatible = "nxp,ftm";
293			reg = <0x4006f000 0x1000>;
294			interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <134 0>;
295			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
296			clocks = <&clock NXP_S32_CORE_CLK>;
297			prescaler = <1>;
298			status = "disabled";
299		};
300
301		ftm6: ftm@40070000 {
302			compatible = "nxp,ftm";
303			reg = <0x40070000 0x1000>;
304			interrupts = <135 0>, <136 0>, <137 0>, <138 0>, <140 0>;
305			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
306			clocks = <&clock NXP_S32_CORE_CLK>;
307			prescaler = <1>;
308			status = "disabled";
309		};
310
311		ftm7: ftm@40071000 {
312			compatible = "nxp,ftm";
313			reg = <0x40071000 0x1000>;
314			interrupts = <141 0>, <142 0>, <143 0>, <144 0>, <146 0>;
315			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
316			clocks = <&clock NXP_S32_CORE_CLK>;
317			prescaler = <1>;
318			status = "disabled";
319		};
320
321		rtc: rtc@4003d000 {
322			compatible = "nxp,rtc";
323			reg = <0x4003d000 0x1000>;
324			interrupts = <46 0>, <47 0>;
325			interrupt-names = "alarm", "seconds";
326			clock-frequency = <32000>;
327			prescaler = <32000>;
328		};
329
330		adc0: adc@4003b000 {
331			compatible = "nxp,adc12";
332			reg = <0x4003b000 0x1000>;
333			interrupts = <39 0>;
334			clk-source = <0>;
335			clk-divider = <1>;
336			clocks = <&clock NXP_S32_ADC0_CLK>;
337			#io-channel-cells = <1>;
338			status = "disabled";
339		};
340
341		adc1: adc@40027000 {
342			compatible = "nxp,adc12";
343			reg = <0x40027000 0x1000>;
344			interrupts = <40 0>;
345			clk-source = <0>;
346			clk-divider = <1>;
347			clocks = <&clock NXP_S32_ADC1_CLK>;
348			#io-channel-cells = <1>;
349			status = "disabled";
350		};
351	};
352};
353