Lines Matching +full:0 +full:x40024000
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
43 reg = <0xe000ed90 0x40>;
50 reg = <0x90000000 DT_SIZE_M(256)>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
73 driving-capability = <0>;
78 #clock-cells = <0>;
85 #clock-cells = <0>;
106 reg = <0xa0000000 0x400>;
107 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
113 #size-cells = <0>;
120 reg = <0x40023c00 0x400>;
121 interrupts = <4 0>;
138 reg = <0x40023800 0x400>;
151 reg = <0x40013c00 0x400>;
153 interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
154 <10 0>, <23 0>, <40 0>;
157 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
165 reg = <0x40020000 0x2400>;
171 reg = <0x40020000 0x400>;
172 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
179 reg = <0x40020400 0x400>;
187 reg = <0x40020800 0x400>;
195 reg = <0x40020C00 0x400>;
203 reg = <0x40021000 0x400>;
211 reg = <0x40021400 0x400>;
219 reg = <0x40021800 0x400>;
227 reg = <0x40021C00 0x400>;
235 reg = <0x40022000 0x400>;
242 reg = <0x40003000 0x400>;
248 reg = <0x40002C00 0x400>;
250 interrupts = <0 7>;
256 reg = <0x40011000 0x400>;
259 interrupts = <37 0>;
265 reg = <0x40004400 0x400>;
268 interrupts = <38 0>;
274 reg = <0x40004800 0x400>;
277 interrupts = <39 0>;
283 reg = <0x40004c00 0x400>;
286 interrupts = <52 0>;
292 reg = <0x40005000 0x400>;
295 interrupts = <53 0>;
301 reg = <0x40011400 0x400>;
304 interrupts = <71 0>;
310 reg = <0x40007800 0x400>;
313 interrupts = <82 0>;
319 reg = <0x40007c00 0x400>;
322 interrupts = <83 0>;
330 #size-cells = <0>;
331 reg = <0x40005400 0x400>;
333 interrupts = <31 0>, <32 0>;
342 #size-cells = <0>;
343 reg = <0x40005800 0x400>;
345 interrupts = <33 0>, <34 0>;
354 #size-cells = <0>;
355 reg = <0x40005c00 0x400>;
357 interrupts = <72 0>, <73 0>;
365 #size-cells = <0>;
366 reg = <0x40013000 0x400>;
375 #size-cells = <0>;
376 reg = <0x40003800 0x400>;
385 #size-cells = <0>;
386 reg = <0x40003c00 0x400>;
395 #size-cells = <0>;
396 reg = <0x40013400 0x400>;
405 #size-cells = <0>;
406 reg = <0x40015000 0x400>;
414 reg = <0x40006400 0x400>;
415 interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
423 reg = <0x40010000 0x400>;
424 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
425 resets = <&rctl STM32_RESET(APB2, 0U)>;
426 interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
428 st,prescaler = <0>;
440 reg = <0x40000000 0x400>;
441 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
442 resets = <&rctl STM32_RESET(APB1, 0U)>;
443 interrupts = <28 0>;
445 st,prescaler = <0>;
462 reg = <0x40000400 0x400>;
465 interrupts = <29 0>;
467 st,prescaler = <0>;
484 reg = <0x40000800 0x400>;
487 interrupts = <30 0>;
489 st,prescaler = <0>;
506 reg = <0x40000c00 0x400>;
509 interrupts = <50 0>;
511 st,prescaler = <0>;
528 reg = <0x40001000 0x400>;
531 interrupts = <54 0>;
533 st,prescaler = <0>;
544 reg = <0x40001400 0x400>;
547 interrupts = <55 0>;
549 st,prescaler = <0>;
560 reg = <0x40010400 0x400>;
563 interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
565 st,prescaler = <0>;
577 reg = <0x40014000 0x400>;
580 interrupts = <24 0>;
582 st,prescaler = <0>;
599 reg = <0x40014400 0x400>;
602 interrupts = <25 0>;
604 st,prescaler = <0>;
621 reg = <0x40014800 0x400>;
624 interrupts = <26 0>;
626 st,prescaler = <0>;
643 reg = <0x40001800 0x400>;
646 interrupts = <43 0>;
648 st,prescaler = <0>;
665 reg = <0x40001c00 0x400>;
668 interrupts = <44 0>;
670 st,prescaler = <0>;
687 reg = <0x40002000 0x400>;
690 interrupts = <45 0>;
692 st,prescaler = <0>;
709 reg = <0x50000000 0x40000>;
710 interrupts = <67 0>;
717 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
723 reg = <0x40040000 0x40000>;
724 interrupts = <77 0>, <74 0>, <75 0>;
730 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
737 reg = <0x40002800 0x300>;
738 interrupts = <41 0>;
754 reg = <0x40012000 0x50>;
756 interrupts = <18 0>;
759 resolutions = <STM32_ADC_RES(12, 0x00)
760 STM32_ADC_RES(10, 0x01)
761 STM32_ADC_RES(8, 0x02)
762 STM32_ADC_RES(6, 0x03)>;
771 reg = <0x40012100 0x50>;
773 interrupts = <18 0>;
776 resolutions = <STM32_ADC_RES(12, 0x00)
777 STM32_ADC_RES(10, 0x01)
778 STM32_ADC_RES(8, 0x02)
779 STM32_ADC_RES(6, 0x03)>;
788 reg = <0x40012200 0x50>;
790 interrupts = <18 0>;
793 resolutions = <STM32_ADC_RES(12, 0x00)
794 STM32_ADC_RES(10, 0x01)
795 STM32_ADC_RES(8, 0x02)
796 STM32_ADC_RES(6, 0x03)>;
805 reg = <0x40007400 0x400>;
814 reg = <0x40026000 0x400>;
815 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
823 reg = <0x40026400 0x400>;
824 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
832 reg = <0x50060800 0x400>;
833 interrupts = <80 0>;
835 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
841 reg = <0x40012c00 0x400>;
843 <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;
845 interrupts = <49 0>;
851 reg = <0x40024000 DT_SIZE_K(4)>;
859 #address-cells = <0x1>;
860 #size-cells = <0x0>;
861 reg = <0xa0001000 0x34>;
862 interrupts = <92 0>;
870 ts-cal1-addr = <0x1FF0F44C>;
871 ts-cal2-addr = <0x1FF0F44E>;
881 vrefint-cal-addr = <0x1FF0F44A>;
896 #phy-cells = <0>;
901 #phy-cells = <0>;
907 #size-cells = <0>;
915 #size-cells = <0>;
923 #size-cells = <0>;