Lines Matching +full:0 +full:x40024000
15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0xB0000>;
78 reg = <0x52000000 0x2000000>;
84 reg = <0x54000000 0x2000000>;
90 reg = <0x56000000 0x2000000>;
99 reg = <0x0000c000 0x1f4000>;
107 reg = <0x0000c000 0x1f4000>;
113 reg = <0x40021000 0x400>;
119 reg = <0x40008140 0x80>;
120 interrupts = <23 0>;
126 reg = <0x40008000 0x20>;
127 interrupts = <14 0>;
135 reg = <0x40008020 0x20>;
136 interrupts = <14 0>;
144 reg = <0x40008040 0x20>;
145 interrupts = <14 0>;
153 reg = <0x40008060 0x20>;
154 interrupts = <14 0>;
162 reg = <0x40008080 0x20>;
163 interrupts = <14 0>;
171 reg = <0x400080A0 0x20>;
172 interrupts = <14 0>;
180 reg = <0x400080C0 0x20>;
181 interrupts = <14 0>;
189 reg = <0x400080E0 0x20>;
190 interrupts = <14 0>;
198 reg = <0x4001c000 0x1000>;
199 interrupts = <15 0>;
203 ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
209 reg = <0x4001d000 0x1000>;
210 interrupts = <16 0>;
214 ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
220 reg = <0x50000100 0x1000>;
222 #size-cells = <0>;
223 interrupts = <4 0>;
225 ambiq,pwrcfg = <&pwrcfg 0x8 0>;
230 reg = <0x50004000 0x1000>;
232 #size-cells = <0>;
233 interrupts = <6 0>;
235 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
240 reg = <0x50005000 0x1000>;
242 #size-cells = <0>;
243 interrupts = <7 0>;
245 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
250 reg = <0x50006000 0x1000>;
252 #size-cells = <0>;
253 interrupts = <8 0>;
255 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
260 reg = <0x50007000 0x1000>;
262 #size-cells = <0>;
263 interrupts = <9 0>;
265 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
270 reg = <0x50008000 0x1000>;
272 #size-cells = <0>;
273 interrupts = <10 0>;
275 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
280 reg = <0x50009000 0x1000>;
282 #size-cells = <0>;
283 interrupts = <11 0>;
285 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
290 reg = <0x50004000 0x1000>;
292 #size-cells = <0>;
293 interrupts = <6 0>;
295 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
300 reg = <0x50005000 0x1000>;
302 #size-cells = <0>;
303 interrupts = <7 0>;
305 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
310 reg = <0x50006000 0x1000>;
312 #size-cells = <0>;
313 interrupts = <8 0>;
315 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
320 reg = <0x50007000 0x1000>;
322 #size-cells = <0>;
323 interrupts = <9 0>;
325 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
330 reg = <0x50008000 0x1000>;
332 #size-cells = <0>;
333 interrupts = <10 0>;
335 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
340 reg = <0x50009000 0x1000>;
342 #size-cells = <0>;
343 interrupts = <11 0>;
345 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
350 reg = <0x50010000 0x400>;
351 interrupts = <18 0>;
357 ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
362 reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
364 interrupts = <20 0>;
366 #size-cells = <0>;
368 ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
373 reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
375 interrupts = <32 0>;
377 #size-cells = <0>;
379 ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
385 reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
386 interrupts = <33 0>;
388 #size-cells = <0>;
390 ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
395 reg = <0x40004240 0xD0>;
396 interrupts = <2 0>;
403 reg = <0x5000c000 0x414>;
406 #size-cells = <0>;
408 ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
410 bt_hci_apollo: bt-hci@0 {
413 reg = <0>;
419 reg = <0x40010000 0x800>;
421 #size-cells = <0>;
425 gpio-map-mask = <0xffffffe0 0xffffffc0>;
426 gpio-map-pass-thru = <0x1f 0x3f>;
428 0x00 0x0 &gpio0_31 0x0 0x0
429 0x20 0x0 &gpio32_63 0x0 0x0
430 0x40 0x0 &gpio64_95 0x0 0x0
432 reg = <0x40010000>;
435 #size-cells = <0>;
438 gpio0_31: gpio0_31@0 {
442 reg = <0>;
443 interrupts = <13 0>;
451 reg = <0x20>;
452 interrupts = <13 0>;
460 reg = <0x40>;
461 interrupts = <13 0>;
470 reg = <0x40024000 0x400>;
471 interrupts = <1 0>;