Lines Matching +full:0 +full:x40024000
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
71 reg = <0x4000051c 0x1>;
79 reg = <0x40000520 0x1>;
85 reg = <0x40000578 0x1>;
93 reg = <0x40000000 0x1000>;
99 reg = <0x40001000 0x1000>;
117 reg = <0x40002000 0x1000>;
132 #size-cells = <0>;
133 reg = <0x40003000 0x1000>;
150 #size-cells = <0>;
151 reg = <0x40003000 0x1000>;
168 #size-cells = <0>;
169 reg = <0x40004000 0x1000>;
186 #size-cells = <0>;
187 reg = <0x40004000 0x1000>;
196 reg = <0x40005000 0x1000>;
203 reg = <0x40006000 0x1000>;
206 instance = <0>;
211 reg = <0x40007000 0x1000>;
220 reg = <0x40008000 0x1000>;
224 prescaler = <0>;
230 reg = <0x40009000 0x1000>;
234 prescaler = <0>;
240 reg = <0x4000a000 0x1000>;
244 prescaler = <0>;
249 reg = <0x4000b000 0x1000>;
259 reg = <0x4000c000 0x1000>;
266 reg = <0x4000d000 0x1000>;
273 reg = <0x4000e000 0x1000>;
280 reg = <0x4000f000 0x1000>;
288 reg = <0x40010000 0x1000>;
295 reg = <0x40011000 0x1000>;
305 reg = <0x40012000 0x1000>;
316 reg = <0x40013000 0x1000>;
323 reg = <0x40014000 0x1000>;
330 reg = <0x40015000 0x1000>;
337 reg = <0x40016000 0x1000>;
344 reg = <0x40017000 0x1000>;
351 reg = <0x40018000 0x1000>;
358 reg = <0x40019000 0x1000>;
366 reg = <0x4001a000 0x1000>;
370 prescaler = <0>;
376 reg = <0x4001b000 0x1000>;
380 prescaler = <0>;
385 reg = <0x4001c000 0x1000>;
393 reg = <0x4001d000 0x1000>;
400 reg = <0x4001e000 0x1000>;
406 flash0: flash@0 {
415 reg = <0x4001f000 0x1000>;
421 reg = <0x40020000 0x1000>;
427 reg = <0x40021000 0x1000>;
435 reg = <0x40022000 0x1000>;
451 #size-cells = <0>;
452 reg = <0x40023000 0x1000>;
461 reg = <0x40024000 0x1000>;
472 #size-cells = <0>;
473 reg = <0x40025000 0x1000>;
481 reg = <0x50000000 0x1000>;
484 port = <0>;