Lines Matching +full:0 +full:x40024000

33 		#size-cells = <0>;
35 		cpu0: cpu@0 {
37 			reg = <0>;
52 			#clock-cells = <0>;
53 			#address-cells = <0>;
61 			#clock-cells = <0>;
69 			#clock-cells = <0>;
77 			#clock-cells = <0>;
85 			#clock-cells = <0>;
93 			#clock-cells = <0>;
101 			#clock-cells = <0>;
109 			#clock-cells = <0>;
117 			#clock-cells = <0>;
125 			#clock-cells = <0>;
136 			#clock-cells = <0>;
147 			#clock-cells = <0>;
154 			stage-drive-strength = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
156 			phase = <0>;
157 			#clock-cells = <0>;
165 			#clock-cells = <0>;
171 			#clock-cells = <0>;
177 			clock-frequency = <0>;
178 			#clock-cells = <0>;
184 			clock-frequency = <0>;
185 			#clock-cells = <0>;
194 			reg = <0x20000000 DT_SIZE_K(264)>;
199 			reg = <0x18000000 0xfc>;
213 			reg = <0x4000c000 DT_SIZE_K(4)>;
215 			active-low = <0>;
221 			reg = <0x40008000 DT_SIZE_K(4)
222 			       0x40024000 DT_SIZE_K(4)
223 			       0x40028000 DT_SIZE_K(4)
224 			       0x4002c000 DT_SIZE_K(4)
225 			       0x40060000 DT_SIZE_K(4)>;
243 			reg = <0x40014000 DT_SIZE_K(4)>;
253 			reg = <0x40034000 DT_SIZE_K(4)>;
263 			reg = <0x40038000 DT_SIZE_K(4)>;
274 			#size-cells = <0>;
275 			reg = <0x4003c000 DT_SIZE_K(4)>;
286 			#size-cells = <0>;
287 			reg = <0x40040000 DT_SIZE_K(4)>;
297 			reg = <0x4004c000 DT_SIZE_K(4)>;
309 			#size-cells = <0>;
310 			reg = <0x40044000 DT_SIZE_K(4)>;
321 			#size-cells = <0>;
322 			reg = <0x40048000 DT_SIZE_K(4)>;
332 			reg = <0x40058000 DT_SIZE_K(4)>;
339 			reg = <0x50110000 0x10000>;
350 			reg = <0x40050000 DT_SIZE_K(4)>;
361 			reg = <0x40054000 DT_SIZE_K(4)>;
364 			interrupts = <0 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
377 			reg = <0x50000000 DT_SIZE_K(64)>;
390 			reg = <0x40064000 1>;
398 			reg = <0x50200000 DT_SIZE_K(4)>;
406 			reg = <0x50300000 DT_SIZE_K(4)>;
414 			reg = <0x4005c000 DT_SIZE_K(4)>;