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/Zephyr-latest/dts/arm/nordic/
Dnrf51822.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
28 reg = <0x10000000 0x1000>;
35 reg = <0x10001000 0x1000>;
45 reg = <0x40000000 0x1000>;
46 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
55 reg = <0x4000051c 0x1>;
62 reg = <0x40000000 0x1000>;
63 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf91_peripherals.dtsi9 reg = <0x39000 0x1000>;
16 flash0: flash@0 {
25 reg = <0xe000 0x1000>;
33 reg = <0x17000 0x1000>;
39 reg = <0x1b000 0x1000>;
46 reg = <0x1c000 0x1000>;
53 reg = <0x1d000 0x1000>;
60 reg = <0x1e000 0x1000>;
67 reg = <0x1f000 0x1000>;
74 reg = <0x20000 0x1000>;
[all …]
Dnrf5340_cpuapp_peripherals.dtsi9 dcnf: dcnf@0 {
11 reg = <0x0 0x1000>;
17 reg = <0x4000 0x1000>;
21 #clock-cells = <0>;
27 #clock-cells = <0>;
34 reg = <0x4000 0x1000>;
41 reg = <0x4704 0x1>;
49 reg = <0x4904 0x1>;
57 reg = <0x4b00 0x44>;
65 reg = <0x5000 0x1000>;
[all …]
Dnrf52810.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52832.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52840.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52805.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
33 reg = <0x10000000 0x1000>;
40 reg = <0x10001000 0x1000>;
50 reg = <0x40000000 0x1000>;
51 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
57 reg = <0x40000000 0x1000>;
58 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
67 reg = <0x4000051c 0x1>;
[all …]
Dnrf52833.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52820.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf52811.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
[all …]
Dnrf5340_cpunet.dtsi19 #size-cells = <0>;
30 reg = <0xe000ed90 0x40>;
38 reg = <0x01ff0000 0x1000>;
45 reg = <0x01ff8000 0x1000>;
60 reg = <0x41005000 0x1000>;
67 reg = <0x41005000 0x1000>;
77 reg = <0x4100551c 0x1>;
85 reg = <0x41005520 0x1>;
92 reg = <0x41008000 0x1000>;
116 reg = <0x41009000 0x1000>;
[all …]
/Zephyr-latest/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/
Dmps2_an521-common.dtsi10 #clock-cells = <0>;
13 timer0: timer@0 {
15 reg = <0x0 0x1000>;
21 reg = <0x1000 0x1000>;
27 reg = <0x2000 0x1000>;
33 reg = <0x3000 0x1000>;
39 reg = <0x4000 0x1000>;
45 reg = <0x100000 0x1000>;
53 reg = <0x101000 0x1000>;
61 reg = <0x102000 0x1000>;
[all …]
/Zephyr-latest/boards/arm/mps2/
Dmps2_an521-common.dtsi10 #clock-cells = <0>;
13 timer0: timer@0 {
15 reg = <0x0 0x1000>;
21 reg = <0x1000 0x1000>;
27 reg = <0x2000 0x1000>;
33 reg = <0x3000 0x1000>;
39 reg = <0x4000 0x1000>;
45 reg = <0x100000 0x1000>;
53 reg = <0x101000 0x1000>;
61 reg = <0x102000 0x1000>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_s32k1xx.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
22 reg = <0>;
37 reg = <0x4000d000 0x1000>;
43 reg = <0x40020000 0x1000>;
44 interrupts = <18 0>, <19 0>, <21 0>;
53 reg = <0x40024000 0x1000>;
61 reg = <0x40025000 0x1000>;
68 reg = <0x4002b000 0x1000>;
75 reg = <0x4002c000 0x1000>;
[all …]
Dnxp_mcxn94x_common.dtsi17 #size-cells = <0>;
19 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
49 reg = <0x4000000 DT_SIZE_K(96)>;
64 reg = <0x20000000 DT_SIZE_K(416)>;
72 syscon: syscon@0 {
74 reg = <0x0 0x4000>;
84 reg = <0x116000 0x1000>;
90 reg = <0x117000 0x1000>;
[all …]
Dnxp_mcxn23x_common.dtsi17 #size-cells = <0>;
19 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
44 reg = <0x4000000 DT_SIZE_K(96)>;
58 reg = <0x20000000 DT_SIZE_K(256)>;
66 syscon: syscon@0 {
68 reg = <0x0 0x4000>;
78 reg = <0x116000 0x1000>;
84 reg = <0x117000 0x1000>;
[all …]
Dnxp_mcxa156.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
20 reg = <0>;
35 reg = <0x40000000 0x4000>;
45 reg = <0x4000000 DT_SIZE_K(8)>;
50 reg = <0x20000000 DT_SIZE_K(120)>;
55 reg = <0x400bc000 0x1000>;
61 reg = <0x400bd000 0x1000>;
67 reg = <0x400be000 0x1000>;
73 reg = <0x400bf000 0x1000>;
[all …]
Dnxp_k8x.dtsi26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
44 reg = <0x4000d000 0x1000>;
50 reg = <0x40047000 0x2000>;
57 #clock-cells = <0>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
84 reg = <0x40064000 0x1000>;
[all …]
Dnxp_kv5x.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
39 reg = <0x4000d000 0x1000>;
45 reg = <0x40047000 0x2000>;
52 #clock-cells = <0>;
59 #clock-cells = <0>;
66 #clock-cells = <0>;
73 #clock-cells = <0>;
79 reg = <0x40064000 0x1000>;
[all …]
Dnxp_rt5xx_common.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
36 reg = <0xe000ed90 0x40>;
45 min-residency-us = <0>;
46 exit-latency-us = <0>;
60 deep-sleep-config = <0xC800>,
61 <0x80000004>,
62 <0xFFFFFFFF>,
63 <0>;
[all …]
/Zephyr-latest/dts/common/nordic/
Dnrf54l_05_10_15.dtsi15 #define NRF_DOMAIN_ID_APPLICATION 0
24 #size-cells = <0>;
26 cpuapp: cpu@0 {
28 reg = <0>;
35 reg = <0xe0000000 0x1000>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
79 reg = <0xffd000 0x1000>;
84 reg = <0xffc000 0x1000>;
[all …]
Dnrf54l20.dtsi20 #size-cells = <0>;
22 cpuapp: cpu@0 {
24 reg = <0>;
31 reg = <0xe0000000 0x1000>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
63 reg = <0xffc000 0x1000>;
69 reg = <0xffd000 0x1000>;
74 reg = <0x20000000 DT_SIZE_K(511)>;
[all …]
Dnrf9280.dtsi23 #size-cells = <0>;
51 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
69 nordic,tasks-mask = <0x0000fff0>;
79 reg = <0xe6b7000 DT_SIZE_K(40)>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
103 reg = <0xe000000 DT_SIZE_K(8192)>;
110 reg = <0xfff8000 DT_SIZE_K(2)>;
116 reg = <0xfffa000 DT_SIZE_K(2)>;
122 reg = <0xfffe000 DT_SIZE_K(2)>;
[all …]
Dnrf54h20.dtsi26 #size-cells = <0>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
77 nordic,tasks-mask = <0xfffffff0>;
93 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
127 nordic,tasks-mask = <0xffff0000>;
132 // substate-id = <0>; is reserved for "idle", cache powered on
155 reg = <0xe1ed000 DT_SIZE_K(20)>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
176 #clock-cells = <0>;
[all …]
/Zephyr-latest/boards/arm/v2m_beetle/
Dv2m_beetle.dts24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
35 reg = <0x20000000 0x20000>;
38 flash0: flash@0 {
40 reg = <0 0x40000>;
46 #clock-cells = <0>;
52 reg = <0x40000000 0x1000>;
59 reg = <0x40001000 0x1000>;
66 reg = <0x40002000 0x1000>;
[all …]

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