Lines Matching +full:0 +full:x1000
15 #define NRF_DOMAIN_ID_APPLICATION 0
24 #size-cells = <0>;
26 cpuapp: cpu@0 {
28 reg = <0>;
35 reg = <0xe0000000 0x1000>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
79 reg = <0xffd000 0x1000>;
84 reg = <0xffc000 0x1000>;
98 ranges = <0x0 0x40000000 0x10000000>;
103 ranges = <0x0 0x50000000 0x10000000>;
108 reg = <0x42000 0x808>;
114 reg = <0x43000 0x1000>;
120 reg = <0x44000 0x1000>;
133 #size-cells = <0>;
134 reg = <0x4a000 0x1000>;
145 reg = <0x4a000 0x1000>;
155 reg = <0x4c000 0x1000>;
156 ranges = <0x0 0x4c000 0x1000>;
163 reg = <0xf0000000 0x1780>;
174 reg = <0x50400 0x300>;
184 reg = <0x55000 0x1000>;
189 prescaler = <0>;
194 reg = <0x82000 0x808>;
200 reg = <0x83000 0x1000>;
206 reg = <0x84000 0x1000>;
213 reg = <0x85000 0x1000>;
218 prescaler = <0>;
223 reg = <0x87000 0x1000>;
230 reg = <0x8a000 0x1000>;
255 reg = <0xc2000 0x808>;
261 reg = <0xc3000 0x1000>;
267 reg = <0xc4000 0x1000>;
273 reg = <0xc5000 0x1000>;
280 #size-cells = <0>;
281 reg = <0xc6000 0x1000>;
297 #size-cells = <0>;
298 reg = <0xc6000 0x1000>;
309 reg = <0xc6000 0x1000>;
319 #size-cells = <0>;
320 reg = <0xc7000 0x1000>;
336 #size-cells = <0>;
337 reg = <0xc7000 0x1000>;
348 reg = <0xc7000 0x1000>;
358 #size-cells = <0>;
359 reg = <0xc8000 0x1000>;
375 #size-cells = <0>;
376 reg = <0xc8000 0x1000>;
387 reg = <0xc8000 0x1000>;
396 reg = <0xc9000 0x1000>;
404 reg = <0xca000 0x1000>;
408 prescaler = <0>;
414 reg = <0xcb000 0x1000>;
418 prescaler = <0>;
424 reg = <0xcc000 0x1000>;
428 prescaler = <0>;
434 reg = <0xcd000 0x1000>;
438 prescaler = <0>;
444 reg = <0xce000 0x1000>;
448 prescaler = <0>;
454 reg = <0xd0000 0x1000>;
461 reg = <0xd1000 0x1000>;
468 reg = <0xd2000 0x1000>;
476 reg = <0xd3000 0x1000>;
484 reg = <0xd4000 0x1000>;
491 reg = <0xd5000 0x1000>;
499 reg = <0xd6000 0x1000>;
506 reg = <0xd7000 0x1000>;
514 reg = <0xd8200 0x300>;
524 reg = <0xda000 0x1000>;
532 #size-cells = <0>;
533 reg = <0xdd000 0x1000>;
540 reg = <0xe0000 0x1000>;
547 reg = <0xe1000 0x1000>;
554 reg = <0xe2000 0x1000>;
561 reg = <0x102000 0x808>;
567 reg = <0x103000 0x1000>;
574 #size-cells = <0>;
575 reg = <0x104000 0x1000>;
591 #size-cells = <0>;
592 reg = <0x104000 0x1000>;
603 reg = <0x104000 0x1000>;
612 reg = <0x10e000 0x1000>;
619 reg = <0x10e000 0x1000>;
620 ranges = <0x0 0x10e000 0x1000>;
630 reg = <0x51c 0x1>;
638 reg = <0x520 0x1>;
649 reg = <0x106000 0x1000>;
659 reg = <0x108000 0x620>;
667 reg = <0x109000 0x620>;
675 reg = <0x10a000 0x300>;
679 port = <0>;
685 reg = <0x10c000 0x1000>;
692 reg = <0x120000 0x1000>;
699 reg = <0x120600 0x1>;
709 reg = <0x5004b000 0x1000>;
714 cpuapp_rram: rram@0 {
728 reg = <0xe000e100 0xc00>;
736 reg = <0xe000e010 0x10>;