Lines Matching +full:0 +full:x1000
20 #size-cells = <0>;
22 cpuapp: cpu@0 {
24 reg = <0>;
31 reg = <0xe0000000 0x1000>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
63 reg = <0xffc000 0x1000>;
69 reg = <0xffd000 0x1000>;
74 reg = <0x20000000 DT_SIZE_K(511)>;
77 ranges = <0x0 0x20000000 0x7fc00>;
81 ranges = <0x0 0x50000000 0x10000000>;
87 reg = <0x42000 0x808>;
93 reg = <0x44000 0x1000>;
99 reg = <0x45000 0x1000>;
112 #size-cells = <0>;
113 reg = <0x4d000 0x1000>;
124 reg = <0x4d000 0x1000>;
135 reg = <0x50400 0x300>;
145 reg = <0x55000 0x1000>;
151 prescaler = <0>;
156 reg = <0x82000 0x808>;
162 reg = <0x83000 0x1000>;
168 reg = <0x84000 0x1000>;
175 reg = <0x85000 0x1000>;
180 prescaler = <0>;
185 reg = <0x87000 0x1000>;
192 reg = <0x8a000 0x1000>;
216 reg = <0xc2000 0x808>;
222 reg = <0xc3000 0x1000>;
228 reg = <0xc4000 0x1000>;
234 reg = <0xc5000 0x1000>;
241 #size-cells = <0>;
242 reg = <0xc6000 0x1000>;
258 #size-cells = <0>;
259 reg = <0xc6000 0x1000>;
270 reg = <0xc6000 0x1000>;
280 #size-cells = <0>;
281 reg = <0xc7000 0x1000>;
297 #size-cells = <0>;
298 reg = <0xc7000 0x1000>;
309 reg = <0xc7000 0x1000>;
319 #size-cells = <0>;
320 reg = <0xc8000 0x1000>;
336 #size-cells = <0>;
337 reg = <0xc8000 0x1000>;
348 reg = <0xc8000 0x1000>;
357 reg = <0xc9000 0x1000>;
365 reg = <0xca000 0x1000>;
369 prescaler = <0>;
375 reg = <0xcb000 0x1000>;
379 prescaler = <0>;
385 reg = <0xcc000 0x1000>;
389 prescaler = <0>;
395 reg = <0xcd000 0x1000>;
399 prescaler = <0>;
405 reg = <0xce000 0x1000>;
409 prescaler = <0>;
415 reg = <0xd0000 0x1000>;
422 reg = <0xd1000 0x1000>;
429 reg = <0xd2000 0x1000>;
437 reg = <0xd3000 0x1000>;
445 reg = <0xd4000 0x1000>;
452 reg = <0xd5000 0x1000>;
460 reg = <0xd6000 0x1000>;
467 reg = <0xd7000 0x1000>;
475 reg = <0xd8200 0x300>;
485 reg = <0xda000 0x1000>;
492 reg = <0xe0000 0x1000>;
499 reg = <0xe1000 0x1000>;
506 reg = <0xe2000 0x1000>;
514 #size-cells = <0>;
515 reg = <0xed000 0x1000>;
531 #size-cells = <0>;
532 reg = <0xed000 0x1000>;
543 reg = <0xed000 0x1000>;
553 #size-cells = <0>;
554 reg = <0xee000 0x1000>;
570 #size-cells = <0>;
571 reg = <0xee000 0x1000>;
582 reg = <0xee000 0x1000>;
591 reg = <0x102000 0x808>;
597 reg = <0x103000 0x1000>;
604 #size-cells = <0>;
605 reg = <0x104000 0x1000>;
621 #size-cells = <0>;
622 reg = <0x104000 0x1000>;
633 reg = <0x104000 0x1000>;
642 reg = <0x108000 0x620>;
649 reg = <0x109000 0x620>;
657 reg = <0x10a000 0x300>;
661 port = <0>;
667 reg = <0x10c000 0x1000>;
674 reg = <0x10e000 0x1000>;
681 reg = <0x120000 0x1000>;
688 reg = <0x120600 0x1>;
698 reg = <0x5004e000 0x1000>;
703 cpuapp_rram: rram@0 {
705 reg = <0x0 DT_SIZE_K(2028)>;
718 reg = <0xe000e100 0xc00>;
726 reg = <0xe000e010 0x10>;