1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <arm/armv8-m.dtsi>
12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13
14/ {
15	cpus: cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			compatible = "arm,cortex-m33f";
21			reg = <0>;
22			#address-cells = <1>;
23			#size-cells = <1>;
24
25			mpu: mpu@e000ed90 {
26				compatible = "arm,armv8m-mpu";
27				reg = <0xe000ed90 0x40>;
28			};
29		};
30		cpu@1 {
31			compatible = "arm,cortex-m33";
32			reg = <1>;
33		};
34	};
35
36	/* Dummy pinctrl node, filled with pin mux options at board level */
37	pinctrl: pinctrl {
38		compatible = "nxp,port-pinctrl";
39		status = "okay";
40	};
41};
42
43&sram {
44	#address-cells = <1>;
45	#size-cells = <1>;
46
47	sramx: memory@4000000 {
48		compatible =  "zephyr,memory-region", "mmio-sram";
49		reg = <0x4000000 DT_SIZE_K(96)>;
50		zephyr,memory-region = "SRAM1";
51		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
52	};
53
54	/* mcxn94x Memory configurations:
55	 *
56	 * RAM blocks RAMA through SRAM4 are contiguous address ranges
57	 *
58	 * MCXN94X: 512KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
59	 *                     RAMC: 64K, RAMD: 64K, RAME: 64K
60	 *                     RAMF: 64K, RAMG: 64K, RAMH: 32K
61	 */
62	sram0: memory@20000000 {
63		compatible = "mmio-sram";
64		reg = <0x20000000 DT_SIZE_K(416)>;
65	};
66};
67
68&peripheral {
69	#address-cells = <1>;
70	#size-cells = <1>;
71
72	syscon: syscon@0 {
73		compatible = "nxp,lpc-syscon";
74		reg = <0x0 0x4000>;
75		#clock-cells = <1>;
76		reset: reset {
77			compatible = "nxp,lpc-syscon-reset";
78			#reset-cells = <1>;
79		};
80	};
81
82	porta: pinmux@116000 {
83		compatible = "nxp,port-pinmux";
84		reg = <0x116000 0x1000>;
85		clocks = <&syscon MCUX_PORT0_CLK>;
86	};
87
88	portb: pinmux@117000 {
89		compatible = "nxp,port-pinmux";
90		reg = <0x117000 0x1000>;
91		clocks = <&syscon MCUX_PORT1_CLK>;
92	};
93
94	portc: pinmux@118000 {
95		compatible = "nxp,port-pinmux";
96		reg = <0x118000 0x1000>;
97		clocks = <&syscon MCUX_PORT2_CLK>;
98	};
99
100	portd: pinmux@119000 {
101		compatible = "nxp,port-pinmux";
102		reg = <0x119000 0x1000>;
103		clocks = <&syscon MCUX_PORT3_CLK>;
104	};
105
106	porte: pinmux@11a000 {
107		compatible = "nxp,port-pinmux";
108		reg = <0x11a000 0x1000>;
109		clocks = <&syscon MCUX_PORT4_CLK>;
110	};
111
112	portf: pinmux@42000 {
113		compatible = "nxp,port-pinmux";
114		reg = <0x42000 0x1000>;
115		clocks = <&syscon MCUX_PORT5_CLK>;
116	};
117
118	gpio0: gpio@96000 {
119		compatible = "nxp,kinetis-gpio";
120		status = "disabled";
121		reg = <0x96000 0x1000>;
122		interrupts = <17 0>,<18 0>;
123		gpio-controller;
124		#gpio-cells = <2>;
125		nxp,kinetis-port = <&porta>;
126	};
127
128	gpio1: gpio@98000 {
129		compatible = "nxp,kinetis-gpio";
130		status = "disabled";
131		reg = <0x98000 0x1000>;
132		interrupts = <19 0>,<20 0>;
133		gpio-controller;
134		#gpio-cells = <2>;
135		nxp,kinetis-port = <&portb>;
136	};
137
138	gpio2: gpio@9a000 {
139		compatible = "nxp,kinetis-gpio";
140		status = "disabled";
141		reg = <0x9a000 0x1000>;
142		interrupts = <21 0>,<22 0>;
143		gpio-controller;
144		#gpio-cells = <2>;
145		nxp,kinetis-port = <&portc>;
146	};
147
148	gpio3: gpio@9c000 {
149		compatible = "nxp,kinetis-gpio";
150		status = "disabled";
151		reg = <0x9c000 0x1000>;
152		interrupts = <23 0>,<24 0>;
153		gpio-controller;
154		#gpio-cells = <2>;
155		nxp,kinetis-port = <&portd>;
156	};
157
158	gpio4: gpio@9e000 {
159		compatible = "nxp,kinetis-gpio";
160		status = "disabled";
161		reg = <0x9e000 0x1000>;
162		interrupts = <25 0>,<26 0>;
163		gpio-controller;
164		#gpio-cells = <2>;
165		nxp,kinetis-port = <&porte>;
166	};
167
168	gpio5: gpio@40000 {
169		compatible = "nxp,kinetis-gpio";
170		status = "disabled";
171		reg = <0x40000 0x1000>;
172		interrupts = <27 0>,<28 0>;
173		gpio-controller;
174		#gpio-cells = <2>;
175		nxp,kinetis-port = <&portf>;
176	};
177
178	flexcomm0: flexcomm@92000 {
179		compatible = "nxp,lp-flexcomm";
180		reg = <0x92000 0x1000>;
181		interrupts = <35 0>;
182		status = "disabled";
183
184		/* Empty ranges property implies parent and child address space is identical */
185		ranges = <>;
186		#address-cells = <1>;
187		#size-cells = <1>;
188
189		flexcomm0_lpuart0: lpuart@92000 {
190			compatible = "nxp,lpuart";
191			reg = <0x92000 0x1000>;
192			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
193			status = "disabled";
194		};
195		flexcomm0_lpspi0: spi@92000 {
196			compatible = "nxp,lpspi";
197			reg = <0x92000 0x1000>;
198			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
199			#address-cells = <1>;
200			#size-cells = <0>;
201			status = "disabled";
202		};
203		flexcomm0_lpi2c0: lpi2c@92800 {
204			compatible = "nxp,lpi2c";
205			reg = <0x92800 0x1000>;
206			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
207			#address-cells = <1>;
208			#size-cells = <0>;
209			status = "disabled";
210		};
211	};
212
213	flexcomm1: flexcomm@93000 {
214		compatible = "nxp,lp-flexcomm";
215		reg = <0x93000 0x1000>;
216		interrupts = <36 0>;
217		status = "disabled";
218
219		ranges = <>;
220		#address-cells = <1>;
221		#size-cells = <1>;
222
223		flexcomm1_lpuart1: lpuart@93000 {
224			compatible = "nxp,lpuart";
225			reg = <0x93000 0x1000>;
226			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
227			/* DMA channels 0 and 1, muxed to LPUART1 RX and TX */
228			dmas = <&edma0 0 71>, <&edma0 1 72>;
229			dma-names = "rx", "tx";
230			status = "disabled";
231		};
232		flexcomm1_lpspi1: spi@93000 {
233			compatible = "nxp,lpspi";
234			reg = <0x93000 0x1000>;
235			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
236			#address-cells = <1>;
237			#size-cells = <0>;
238			/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
239			dmas = <&edma0 0 71>, <&edma0 1 72>;
240			dma-names = "rx", "tx";
241			status = "disabled";
242		};
243		flexcomm1_lpi2c1: lpi2c@93800 {
244			compatible = "nxp,lpi2c";
245			reg = <0x93800 0x1000>;
246			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
247			#address-cells = <1>;
248			#size-cells = <0>;
249			status = "disabled";
250		};
251	};
252
253	flexcomm2: flexcomm@94000 {
254		compatible = "nxp,lp-flexcomm";
255		reg = <0x94000 0x1000>;
256		interrupts = <37 0>;
257		status = "disabled";
258
259		ranges = <>;
260		#address-cells = <1>;
261		#size-cells = <1>;
262
263		flexcomm2_lpuart2: lpuart@94000 {
264			compatible = "nxp,lpuart";
265			reg = <0x94000 0x1000>;
266			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
267			/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
268			dmas = <&edma0 4 73>, <&edma0 5 74>;
269			dma-names = "rx", "tx";
270			status = "disabled";
271		};
272		flexcomm2_lpspi2: spi@94000 {
273			compatible = "nxp,lpspi";
274			reg = <0x94000 0x1000>;
275			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
276			#address-cells = <1>;
277			#size-cells = <0>;
278			/* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */
279			dmas = <&edma0 4 73>, <&edma0 5 74>;
280			dma-names = "rx", "tx";
281			status = "disabled";
282		};
283		flexcomm2_lpi2c2: lpi2c@94800 {
284			compatible = "nxp,lpi2c";
285			reg = <0x94800 0x1000>;
286			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
287			#address-cells = <1>;
288			#size-cells = <0>;
289			status = "disabled";
290		};
291	};
292
293	flexcomm3: flexcomm@95000 {
294		compatible = "nxp,lp-flexcomm";
295		reg = <0x95000 0x1000>;
296		interrupts = <38 0>;
297		status = "disabled";
298
299		ranges = <>;
300		#address-cells = <1>;
301		#size-cells = <1>;
302
303		flexcomm3_lpuart3: lpuart@95000 {
304			compatible = "nxp,lpuart";
305			reg = <0x95000 0x1000>;
306			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
307			status = "disabled";
308		};
309		flexcomm3_lpspi3: spi@95000 {
310			compatible = "nxp,lpspi";
311			reg = <0x95000 0x1000>;
312			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
313			#address-cells = <1>;
314			#size-cells = <0>;
315			status = "disabled";
316		};
317		flexcomm3_lpi2c3: lpi2c@95800 {
318			compatible = "nxp,lpi2c";
319			reg = <0x95800 0x1000>;
320			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
321			#address-cells = <1>;
322			#size-cells = <0>;
323			status = "disabled";
324		};
325	};
326
327	flexcomm4: flexcomm@b4000 {
328		compatible = "nxp,lp-flexcomm";
329		reg = <0xb4000 0x1000>;
330		interrupts = <39 0>;
331		status = "disabled";
332
333		ranges = <>;
334		#address-cells = <1>;
335		#size-cells = <1>;
336
337		flexcomm4_lpuart4: lpuart@b4000 {
338			compatible = "nxp,lpuart";
339			reg = <0xb4000 0x1000>;
340			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
341			/* DMA channels 2 and 3, muxed to LPUART4 RX and TX */
342			dmas = <&edma0 2 77>, <&edma0 3 78>;
343			dma-names = "rx", "tx";
344			status = "disabled";
345		};
346		flexcomm4_lpspi4: spi@b4000 {
347			compatible = "nxp,lpspi";
348			reg = <0xb4000 0x1000>;
349			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
350			#address-cells = <1>;
351			#size-cells = <0>;
352			/* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */
353			dmas = <&edma0 2 77>, <&edma0 3 78>;
354			dma-names = "rx", "tx";
355			status = "disabled";
356		};
357		flexcomm4_lpi2c4: lpi2c@b4800 {
358			compatible = "nxp,lpi2c";
359			reg = <0xb4800 0x1000>;
360			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
361			#address-cells = <1>;
362			#size-cells = <0>;
363			status = "disabled";
364		};
365	};
366
367	flexcomm5: flexcomm@b5000 {
368		compatible = "nxp,lp-flexcomm";
369		reg = <0xb5000 0x1000>;
370		interrupts = <40 0>;
371		status = "disabled";
372
373		ranges = <>;
374		#address-cells = <1>;
375		#size-cells = <1>;
376
377		flexcomm5_lpuart5: lpuart@b5000 {
378			compatible = "nxp,lpuart";
379			reg = <0xb5000 0x1000>;
380			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
381			status = "disabled";
382		};
383		flexcomm5_lpspi5: spi@b5000 {
384			compatible = "nxp,lpspi";
385			reg = <0xb5000 0x1000>;
386			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
387			#address-cells = <1>;
388			#size-cells = <0>;
389			status = "disabled";
390		};
391		flexcomm5_lpi2c5: lpi2c@b5800 {
392			compatible = "nxp,lpi2c";
393			reg = <0xb5800 0x1000>;
394			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
395			#address-cells = <1>;
396			#size-cells = <0>;
397			status = "disabled";
398		};
399	};
400
401	flexcomm6: flexcomm@b6000 {
402		compatible = "nxp,lp-flexcomm";
403		reg = <0xb6000 0x1000>;
404		interrupts = <41 0>;
405		status = "disabled";
406
407		ranges = <>;
408		#address-cells = <1>;
409		#size-cells = <1>;
410
411		flexcomm6_lpuart6: lpuart@b6000 {
412			compatible = "nxp,lpuart";
413			reg = <0xb6000 0x1000>;
414			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
415			status = "disabled";
416		};
417		flexcomm6_lpspi6: spi@b6000 {
418			compatible = "nxp,lpspi";
419			reg = <0xb6000 0x1000>;
420			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
421			#address-cells = <1>;
422			#size-cells = <0>;
423			status = "disabled";
424		};
425		flexcomm6_lpi2c6: lpi2c@b6800 {
426			compatible = "nxp,lpi2c";
427			reg = <0xb6800 0x1000>;
428			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
429			#address-cells = <1>;
430			#size-cells = <0>;
431			status = "disabled";
432		};
433	};
434
435	flexcomm7: flexcomm@b7000 {
436		compatible = "nxp,lp-flexcomm";
437		reg = <0xb7000 0x1000>;
438		interrupts = <42 0>;
439		status = "disabled";
440
441		ranges = <>;
442		#address-cells = <1>;
443		#size-cells = <1>;
444
445		flexcomm7_lpuart7: lpuart@b7000 {
446			compatible = "nxp,lpuart";
447			reg = <0xb7000 0x1000>;
448			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
449			status = "disabled";
450		};
451		flexcomm7_lpspi7: spi@b7000 {
452			compatible = "nxp,lpspi";
453			reg = <0xb7000 0x1000>;
454			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
455			#address-cells = <1>;
456			#size-cells = <0>;
457			status = "disabled";
458		};
459		flexcomm7_lpi2c7: lpi2c@b7800 {
460			compatible = "nxp,lpi2c";
461			reg = <0xb7800 0x1000>;
462			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
463			#address-cells = <1>;
464			#size-cells = <0>;
465			status = "disabled";
466		};
467	};
468
469	flexcomm8: flexcomm@b8000 {
470		compatible = "nxp,lp-flexcomm";
471		reg = <0xb8000 0x1000>;
472		interrupts = <43 0>;
473		status = "disabled";
474
475		ranges = <>;
476		#address-cells = <1>;
477		#size-cells = <1>;
478
479		flexcomm8_lpuart8: lpuart@b8000 {
480			compatible = "nxp,lpuart";
481			reg = <0xb8000 0x1000>;
482			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
483			status = "disabled";
484		};
485		flexcomm8_lpspi8: spi@b8000 {
486			compatible = "nxp,lpspi";
487			reg = <0xb8000 0x1000>;
488			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
489			#address-cells = <1>;
490			#size-cells = <0>;
491			status = "disabled";
492		};
493		flexcomm8_lpi2c8: lpi2c@b8800 {
494			compatible = "nxp,lpi2c";
495			reg = <0xb8800 0x1000>;
496			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
497			#address-cells = <1>;
498			#size-cells = <0>;
499			status = "disabled";
500		};
501	};
502
503	flexcomm9: flexcomm@b9000 {
504		compatible = "nxp,lp-flexcomm";
505		reg = <0xb9000 0x1000>;
506		interrupts = <44 0>;
507		status = "disabled";
508
509		ranges = <>;
510		#address-cells = <1>;
511		#size-cells = <1>;
512
513		flexcomm9_lpuart9: lpuart@b9000 {
514			compatible = "nxp,lpuart";
515			reg = <0xb9000 0x1000>;
516			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
517			status = "disabled";
518		};
519		flexcomm9_lpspi9: spi@b9000 {
520			compatible = "nxp,lpspi";
521			reg = <0xb9000 0x1000>;
522			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
523			#address-cells = <1>;
524			#size-cells = <0>;
525			status = "disabled";
526		};
527		flexcomm9_lpi2c9: lpi2c@b9800 {
528			compatible = "nxp,lpi2c";
529			reg = <0xb9800 0x1000>;
530			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
531			#address-cells = <1>;
532			#size-cells = <0>;
533			status = "disabled";
534		};
535	};
536
537	edma0: dma-controller@80000 {
538		#dma-cells = <2>;
539		compatible = "nxp,mcux-edma";
540		nxp,version = <4>;
541		dma-channels = <16>;
542		dma-requests = <120>;
543
544		reg = <0x80000 0x1000>;
545		interrupts = <1 0>, <2 0>, <3 0>, <4 0>,
546			<5 0>, <6 0>, <7 0>, <8 0>,
547			<9 0>, <10 0>, <11 0>, <12 0>,
548			<13 0>, <14 0>, <15 0>, <16 0>;
549		no-error-irq;
550		status = "disabled";
551	};
552
553	edma1: dma-controller@a0000 {
554		#dma-cells = <2>;
555		compatible = "nxp,mcux-edma";
556		nxp,version = <4>;
557		dma-channels = <16>;
558		dma-requests = <120>;
559
560		reg = <0xa0000 0x1000>;
561		interrupts = <77 0>, <78 0>, <79 0>, <80 0>,
562			<81 0>, <82 0>, <83 0>, <84 0>,
563			<85 0>, <86 0>, <87 0>, <88 0>,
564			<89 0>, <90 0>, <91 0>, <92 0>;
565		no-error-irq;
566		status = "disabled";
567	};
568
569	fmu: flash-controller@43000 {
570		compatible = "nxp,msf1";
571		reg = <0x43000 0x1000>;
572		interrupts = <138 0>;
573		status = "disabled";
574
575		#address-cells = <1>;
576		#size-cells = <1>;
577
578		flash: flash@0 {
579			compatible = "soc-nv-flash";
580			reg = <0 DT_SIZE_M(2)>;
581			erase-block-size = <8192>;
582			/* MCXN94x ROM Flash API supports writing of 128B pages. */
583			write-block-size = <128>;
584		};
585
586		uuid: uuid@1100000 {
587			compatible = "nxp,lpc-uid";
588			reg = <0x1100000 0x10>;
589		};
590	};
591
592	os_timer: timers@49000 {
593		compatible = "nxp,os-timer";
594		reg = <0x49000 0x1000>;
595		interrupts = <57 0>;
596		status = "disabled";
597	};
598
599	dac0: dac@10f000 {
600		compatible = "nxp,lpdac";
601		reg = < 0x10f000 0x1000>;
602		interrupts = <106 0>;
603		status = "disabled";
604		voltage-reference = <0>;
605		#io-channel-cells = <1>;
606	};
607
608	dac1: dac@112000 {
609		compatible = "nxp,lpdac";
610		reg = < 0x112000 0x1000>;
611		interrupts = <107 0>;
612		status = "disabled";
613		voltage-reference = <0>;
614		#io-channel-cells = <1>;
615	};
616
617	enet: ethernet@40100000 {
618		compatible = "nxp,enet-qos";
619		reg = <0x40100000 0x1200>;
620		clocks = <&syscon MCUX_ENET_QOS_CLK>;
621		enet_mac: ethernet {
622			compatible = "nxp,enet-qos-mac";
623			status = "disabled";
624			interrupts = <139 0>, <140 0>, <141 0>;
625			interrupt-names = "mac", "power", "lpi";
626		};
627		enet_mdio: mdio {
628			#address-cells = <1>;
629			#size-cells = <0>;
630			compatible = "nxp,enet-qos-mdio";
631			status = "disabled";
632		};
633	};
634
635	wwdt0: watchdog@16000 {
636		compatible = "nxp,lpc-wwdt";
637		reg = <0x16000 0x1000>;
638		interrupts = <152 0>;
639		status = "disabled";
640		clk-divider = <1>;
641	};
642
643	flexpwm0: flexpwm@ce000 {
644		compatible = "nxp,flexpwm";
645		reg = <0xce000 0x1000>;
646		interrupt-names = "RELOAD-ERROR", "FAULT";
647		interrupts = <112 0>, <113 0>;
648		flexpwm0_pwm0: pwm0 {
649			compatible = "nxp,imx-pwm";
650			index = <0>;
651			interrupts = <114 0>;
652			#pwm-cells = <3>;
653			clocks = <&syscon MCUX_BUS_CLK>;
654			nxp,prescaler = <128>;
655			status = "disabled";
656			run-in-wait;
657		};
658
659		flexpwm0_pwm1: pwm1 {
660			compatible = "nxp,imx-pwm";
661			index = <1>;
662			interrupts = <115 0>;
663			#pwm-cells = <3>;
664			clocks = <&syscon MCUX_BUS_CLK>;
665			nxp,prescaler = <128>;
666			status = "disabled";
667			run-in-wait;
668		};
669
670		flexpwm0_pwm2: pwm2 {
671			compatible = "nxp,imx-pwm";
672			index = <2>;
673			interrupts = <116 0>;
674			#pwm-cells = <3>;
675			clocks = <&syscon MCUX_BUS_CLK>;
676			nxp,prescaler = <128>;
677			status = "disabled";
678			run-in-wait;
679		};
680
681		flexpwm0_pwm3: pwm3 {
682			compatible = "nxp,imx-pwm";
683			index = <3>;
684			interrupts = <117 0>;
685			#pwm-cells = <3>;
686			clocks = <&syscon MCUX_BUS_CLK>;
687			nxp,prescaler = <128>;
688			status = "disabled";
689			run-in-wait;
690		};
691	};
692
693	flexpwm1: flexpwm@d0000 {
694		compatible = "nxp,flexpwm";
695		reg = <0xd0000 0x1000>;
696		interrupt-names = "RELOAD-ERROR", "FAULT";
697		interrupts = <118 0>, <119 0>;
698		flexpwm1_pwm0: pwm0 {
699			compatible = "nxp,imx-pwm";
700			index = <0>;
701			interrupts = <120 0>;
702			#pwm-cells = <3>;
703			clocks = <&syscon MCUX_BUS_CLK>;
704			nxp,prescaler = <128>;
705			status = "disabled";
706			run-in-wait;
707		};
708
709		flexpwm1_pwm1: pwm1 {
710			compatible = "nxp,imx-pwm";
711			index = <1>;
712			interrupts = <121 0>;
713			#pwm-cells = <3>;
714			clocks = <&syscon MCUX_BUS_CLK>;
715			nxp,prescaler = <128>;
716			status = "disabled";
717			run-in-wait;
718		};
719
720		flexpwm1_pwm2: pwm2 {
721			compatible = "nxp,imx-pwm";
722			index = <2>;
723			interrupts = <122 0>;
724			#pwm-cells = <3>;
725			clocks = <&syscon MCUX_BUS_CLK>;
726			nxp,prescaler = <128>;
727			status = "disabled";
728			run-in-wait;
729		};
730
731		flexpwm1_pwm3: pwm3 {
732			compatible = "nxp,imx-pwm";
733			index = <3>;
734			interrupts = <123 0>;
735			#pwm-cells = <3>;
736			clocks = <&syscon MCUX_BUS_CLK>;
737			nxp,prescaler = <128>;
738			status = "disabled";
739			run-in-wait;
740		};
741	};
742
743	ctimer0: ctimer@c000 {
744		compatible = "nxp,lpc-ctimer";
745		reg = <0xc000 0x1000>;
746		interrupts = <31 0>;
747		status = "disabled";
748		clk-source = <1>;
749		clocks = <&syscon MCUX_CTIMER0_CLK>;
750		mode = <0>;
751		input = <0>;
752		prescale = <0>;
753	};
754
755	ctimer1: ctimer@d000 {
756		compatible = "nxp,lpc-ctimer";
757		reg = <0xd000 0x1000>;
758		interrupts = <32 0>;
759		status = "disabled";
760		clk-source = <1>;
761		clocks = <&syscon MCUX_CTIMER1_CLK>;
762		mode = <0>;
763		input = <0>;
764		prescale = <0>;
765	};
766
767	ctimer2: ctimer@e000 {
768		compatible = "nxp,lpc-ctimer";
769		reg = <0xe000 0x1000>;
770		interrupts = <34 0>;
771		status = "disabled";
772		clk-source = <1>;
773		clocks = <&syscon MCUX_CTIMER2_CLK>;
774		mode = <0>;
775		input = <0>;
776		prescale = <0>;
777	};
778
779	ctimer3: ctimer@f000 {
780		compatible = "nxp,lpc-ctimer";
781		reg = <0xf000 0x1000>;
782		interrupts = <55 0>;
783		status = "disabled";
784		clk-source = <1>;
785		clocks = <&syscon MCUX_CTIMER3_CLK>;
786		mode = <0>;
787		input = <0>;
788		prescale = <0>;
789	};
790
791	ctimer4: ctimer@10000 {
792		compatible = "nxp,lpc-ctimer";
793		reg = <0x10000 0x1000>;
794		interrupts = <56 0>;
795		status = "disabled";
796		clk-source = <1>;
797		clocks = <&syscon MCUX_CTIMER4_CLK>;
798		mode = <0>;
799		input = <0>;
800		prescale = <0>;
801	};
802
803	sc_timer: pwm@91000 {
804		compatible = "nxp,sctimer-pwm";
805		reg = <0x91000 0x1000>;
806		interrupts = <33 0>;
807		clocks = <&syscon MCUX_SCTIMER_CLK>;
808		status = "disabled";
809		prescaler = <1>;
810		#pwm-cells = <3>;
811	};
812
813	smartdma: smartdma@33000 {
814		compatible = "nxp,smartdma";
815		reg = <0x33000 0x1000>;
816		status = "disabled";
817		interrupts = <53 0>;
818		program-mem = <0x4000000>;
819		#dma-cells = <0>;
820	};
821
822	usdhc0: usdhc@109000 {
823		compatible = "nxp,imx-usdhc";
824		reg = <0x109000 0x1000>;
825		interrupts = <61 0>;
826		status = "disabled";
827		clocks = <&syscon MCUX_USDHC1_CLK>;
828		max-bus-freq = <52000000>;
829		min-bus-freq = <400000>;
830	};
831
832	vref: vref@111000 {
833		compatible = "nxp,vref";
834		regulator-name = "mcxn94x-vref";
835		reg = <0x111000 0x14>;
836		status = "disabled";
837		#nxp,reference-cells = <1>;
838		nxp,buffer-startup-delay-us = <400>;
839		nxp,bandgap-startup-time-us = <20>;
840		regulator-min-microvolt = <1000000>;
841		regulator-max-microvolt = <2100000>;
842
843	};
844
845	lpadc0: adc@10d000 {
846		compatible = "nxp,lpc-lpadc";
847		reg = <0x10d000 0x1000>;
848		interrupts = <45 0>;
849		status = "disabled";
850		voltage-ref= <1>;
851		calibration-average = <128>;
852		power-level = <0>;
853		offset-value-a = <0>;
854		offset-value-b = <0>;
855		#io-channel-cells = <1>;
856		clocks = <&syscon MCUX_LPADC1_CLK>;
857		nxp,references = <&vref 1800>;
858	};
859
860	lpadc1: adc@10e000 {
861		compatible = "nxp,lpc-lpadc";
862		reg = <0x10e000 0x1000>;
863		interrupts = <46 0>;
864		status = "disabled";
865		voltage-ref= <0>;
866		calibration-average = <128>;
867		power-level = <1>;
868		offset-value-a = <0>;
869		offset-value-b = <0>;
870		#io-channel-cells = <1>;
871		clocks = <&syscon MCUX_LPADC2_CLK>;
872	};
873
874	usb1: usbd@10b000 {
875		compatible = "nxp,ehci";
876		reg = <0x10b000 0x1000>;
877		interrupts = <67 0>;
878		interrupt-names = "usb_otg";
879		num-bidir-endpoints = <8>;
880		status = "disabled";
881	};
882
883	usbphy1: usbphy@10a000 {
884		compatible = "nxp,usbphy";
885		reg = <0x10a000 0x1000>;
886		status = "disabled";
887	};
888
889	lpcmp0: lpcmp@51000 {
890		compatible = "nxp,lpcmp";
891		reg = <0x51000 0x1000>;
892		interrupts = <109 0>;
893		status = "disabled";
894		#io-channel-cells = <2>;
895	};
896
897	lpcmp1: lpcmp@52000 {
898		compatible = "nxp,lpcmp";
899		reg = <0x52000 0x1000>;
900		interrupts = <110 0>;
901		status = "disabled";
902		#io-channel-cells = <2>;
903	};
904
905	lpcmp2: lpcmp@53000 {
906		compatible = "nxp,lpcmp";
907		reg = <0x53000 0x1000>;
908		interrupts = <111 0>;
909		status = "disabled";
910		#io-channel-cells = <2>;
911	};
912
913	flexcan0: can@d4000 {
914		compatible = "nxp,flexcan";
915		reg = <0xd4000 0x4000>;
916		interrupts = <62 0>;
917		interrupt-names = "common";
918		clocks = <&syscon MCUX_FLEXCAN0_CLK>;
919		clk-source = <0>;
920		status = "disabled";
921	};
922
923	flexcan1: can@d8000 {
924		compatible = "nxp,flexcan";
925		reg = <0xd8000 0x4000>;
926		interrupts = <63 0>;
927		interrupt-names = "common";
928		clocks = <&syscon MCUX_FLEXCAN1_CLK>;
929		clk-source = <0>;
930		status = "disabled";
931	};
932
933	lptmr0: lptmr@4a000 {
934		compatible = "nxp,lptmr";
935		reg = <0x4a000 0x1000>;
936		interrupts = <143 0>;
937		clock-frequency = <16000>;
938		prescaler = <1>;
939		clk-source = <1>;
940		resolution = <32>;
941	};
942
943	lptmr1: lptmr@4b000 {
944		compatible = "nxp,lptmr";
945		reg = <0x4b000 0x1000>;
946		interrupts = <144 0>;
947		clock-frequency = <16000>;
948		prescaler = <1>;
949		clk-source = <1>;
950		resolution = <32>;
951	};
952
953	i3c0: i3c@21000 {
954		compatible = "nxp,mcux-i3c";
955		reg = <0x21000 0x1000>;
956		interrupts = <95 0>;
957		clocks = <&syscon MCUX_I3C_CLK>;
958		clk-divider = <6>;
959		clk-divider-slow = <1>;
960		clk-divider-tc = <1>;
961		status = "disabled";
962		#address-cells = <3>;
963		#size-cells = <0>;
964	};
965
966	i3c1: i3c@22000 {
967		compatible = "nxp,mcux-i3c";
968		reg = <0x22000 0x1000>;
969		interrupts = <96 0>;
970		clocks = <&syscon MCUX_I3C2_CLK>;
971		clk-divider = <6>;
972		clk-divider-slow = <1>;
973		clk-divider-tc = <1>;
974		status = "disabled";
975		#address-cells = <3>;
976		#size-cells = <0>;
977	};
978
979	flexio0: flexio@105000 {
980		compatible = "nxp,flexio";
981		reg = <0x105000 0x1000>;
982		status = "disabled";
983		interrupts = <105 0>;
984		clocks = <&syscon MCUX_FLEXIO0_CLK>;
985		flexio0_lcd: flexio0-lcd {
986			compatible = "nxp,mipi-dbi-flexio-lcdif";
987			status = "disabled";
988		};
989	};
990
991	mrt0: mrt@13000 {
992		compatible = "nxp,mrt";
993		reg = <0x13000 0x1000>;
994		interrupts = <30 0>;
995		num-channels = <4>;
996		num-bits = <24>;
997		clocks = <&syscon MCUX_MRT_CLK>;
998		resets = <&reset NXP_SYSCON_RESET(1, 0)>;
999		#address-cells = <1>;
1000		#size-cells = <0>;
1001
1002		mrt0_channel0: mrt0_channel@0 {
1003			compatible = "nxp,mrt-channel";
1004			reg = <0>;
1005			status = "disabled";
1006		};
1007		mrt0_channel1: mrt0_channel@1 {
1008			compatible = "nxp,mrt-channel";
1009			reg = <1>;
1010			status = "disabled";
1011		};
1012		mrt0_channel2: mrt0_channel@2 {
1013			compatible = "nxp,mrt-channel";
1014			reg = <2>;
1015			status = "disabled";
1016		};
1017		mrt0_channel3: mrt0_channel@3 {
1018			compatible = "nxp,mrt-channel";
1019			reg = <3>;
1020			status = "disabled";
1021		};
1022	};
1023
1024	rtc: rtc@4c000 {
1025		compatible = "nxp,irtc";
1026		reg = <0x4c000 0x1000>;
1027		status = "disabled";
1028		interrupts = <52 0>;
1029		prescaler = <1>;
1030		clock-frequency = <16384>;
1031		clock-src = <0>;
1032		alarms-count = <1>;
1033	};
1034};
1035
1036&systick {
1037	/*
1038	 * MCXN94X relies by default on the OS Timer for system clock
1039	 * implementation, so the SysTick node is not to be enabled.
1040	 */
1041	status = "disabled";
1042};
1043
1044&flexspi {
1045	compatible = "nxp,imx-flexspi";
1046	interrupts = <58 0>;
1047	#address-cells = <1>;
1048	#size-cells = <0>;
1049	status = "disabled";
1050	clocks = <&syscon MCUX_FLEXSPI_CLK>;
1051};
1052
1053&nvic {
1054	arm,num-irq-priority-bits = <3>;
1055};
1056