Lines Matching +full:0 +full:x1000
25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
36 reg = <0xe000ed90 0x40>;
45 min-residency-us = <0>;
46 exit-latency-us = <0>;
60 deep-sleep-config = <0xC800>,
61 <0x80000004>,
62 <0xFFFFFFFF>,
63 <0>;
78 * Note that the sram code region starts at an offset of 0x1B000,
79 * as the boot ROM will not load code before 0x1C000. The first
80 * 0x1000 of the image will contain the boot header.
84 reg = <0x1b000 DT_SIZE_K(1428)>;
89 reg = <0x20180000 DT_SIZE_K(3072)>;
94 reg = <0x40140000 DT_SIZE_K(16)>;
114 * addresses differ between non-secure (0x40000000) and secure
115 * modes (0x50000000).
119 reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
123 reg = <0x13c000 0x1000>, <0x38000000 DT_SIZE_M(128)>;
129 reg = <0x1000 0x1000>;
135 reg = <0x4000 0x1000>;
144 reg = <0x21000 0x1000>;
148 rstctl0: reset@0 {
150 reg = <0x0 0x80>;
156 reg = <0x20000 0x80>;
162 reg = <0x2f50 0x10>;
167 reg = <0x100000 0x2784>;
169 #size-cells = <0>;
171 gpio0: gpio@0 {
176 reg = <0>;
225 reg = <0x25000 0x1000>;
228 #address-cells = <0>;
237 reg = <0x106000 0x1000>;
238 interrupts = <14 0>;
240 resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
246 reg = <0x107000 0x1000>;
247 interrupts = <15 0>;
249 resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
255 reg = <0x108000 0x1000>;
256 interrupts = <16 0>;
258 resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
264 reg = <0x109000 0x1000>;
265 interrupts = <17 0>;
267 resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
273 reg = <0x122000 0x1000>;
274 interrupts = <18 0>;
276 resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>;
282 reg = <0x123000 0x1000>;
283 interrupts = <19 0>;
285 resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>;
291 reg = <0x124000 0x1000>;
292 interrupts = <43 0>;
294 resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>;
300 reg = <0x125000 0x1000>;
301 interrupts = <44 0>;
303 resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>;
309 reg = <0x127000 0x1000>;
310 interrupts = <21 0>;
312 resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>;
318 reg = <0x209000 0x1000>;
319 interrupts = <60 0>;
321 resets = <&rstctl1 NXP_SYSCON_RESET(0, 16)>;
327 reg = <0x20a000 0x1000>;
328 interrupts = <61 0>;
330 resets = <&rstctl1 NXP_SYSCON_RESET(0, 17)>;
336 reg = <0x20b000 0x1000>;
337 interrupts = <62 0>;
339 resets = <&rstctl1 NXP_SYSCON_RESET(0, 18)>;
345 reg = <0x20c000 0x1000>;
346 interrupts = <63 0>;
348 resets = <&rstctl1 NXP_SYSCON_RESET(0, 19)>;
354 reg = <0x20d000 0x1000>;
355 interrupts = <64 0>;
357 resets = <&rstctl1 NXP_SYSCON_RESET(0, 20)>;
363 reg = <0x20e000 0x1000>;
364 interrupts = <65 0>;
366 resets = <&rstctl1 NXP_SYSCON_RESET(0, 21)>;
372 reg = <0x210000 0x1000>;
373 interrupts = <69 0>;
379 reg = <0x144000 0x1000>;
387 reg = <0x126000 0x1000>;
388 interrupts = <20 0>;
390 resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
393 #size-cells = <0>;
398 reg = <0x128000 0x1000>;
399 interrupts = <66 0>;
401 resets = <&rstctl1 NXP_SYSCON_RESET(0, 24)>;
404 #size-cells = <0>;
409 reg = <0x104000 0x1000>;
410 interrupts = <1 0>;
421 reg = <0x105000 0x1000>;
422 interrupts = <54 0>;
433 #size-cells=<0>;
435 reg = <0x121000 0x1000>;
436 interrupts = <25 0>;
440 pdmc0: dmic-channel@0 {
442 reg = <0>;
499 reg = <0x113000 0x1000>;
500 interrupts = <41 0>;
506 reg = <0x30000 0x1000>;
507 interrupts = <32 0>;
517 reg = <0x138000 0x1000>;
519 interrupts = <31 0>;
524 reg = <0x146000 0x1000>;
525 interrupts = <12 0>;
534 reg = <0xe000 0x1000>;
535 interrupts = <0 0>;
542 reg = <0x2e000 0x1000>;
543 interrupts = <52 0>;
550 reg = <0x136000 0x1000>;
552 interrupts = <45 0>;
562 reg = <0x137000 0x1000>;
564 interrupts = <46 0>;
574 reg = <0x13a000 0x304>;
575 interrupts = <22 0>;
579 power-level = <0>;
588 reg = <0x27000 0x1000>;
589 program-mem = <0x24100000>;
590 interrupts = <73 0>;
592 #dma-cells = <0>;
597 reg = <0x28000 0x1000>;
598 interrupts = <10 0>;
602 mode = <0>;
603 input = <0>;
604 prescale = <0>;
609 reg = <0x29000 0x1000>;
610 interrupts = <11 0>;
614 mode = <0>;
615 input = <0>;
616 prescale = <0>;
621 reg = <0x2a000 0x1000>;
622 interrupts = <39 0>;
626 mode = <0>;
627 input = <0>;
628 prescale = <0>;
633 reg = <0x2b000 0x1000>;
634 interrupts = <13 0>;
638 mode = <0>;
639 input = <0>;
640 prescale = <0>;
645 reg = <0x2c000 0x1000>;
646 interrupts = <40 0>;
650 mode = <0>;
651 input = <0>;
652 prescale = <0>;
658 #size-cells = <0>;
659 reg = <0x31000 0x1000>;
660 interrupts = <71 0>;
670 reg = <0x36000 0x1000>;
671 interrupts = <49 0>;
678 #size-cells = <0>;
683 reg = <0x110000 0x100>;
684 interrupts = <34 0>;
692 reg = <0x2d000 0x100>;
693 interrupts = <9 0>;
699 #size-cells = <0>;
701 mrt_channel0: mrt_channel@0 {
703 reg = <0>;
727 interrupts = <42 0>;
729 #size-cells = <0>;
736 interrupts = <42 0>;
738 #size-cells = <0>;