Lines Matching +full:0 +full:x1000
17 #size-cells = <0>;
19 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
44 reg = <0x4000000 DT_SIZE_K(96)>;
58 reg = <0x20000000 DT_SIZE_K(256)>;
66 syscon: syscon@0 {
68 reg = <0x0 0x4000>;
78 reg = <0x116000 0x1000>;
84 reg = <0x117000 0x1000>;
90 reg = <0x118000 0x1000>;
96 reg = <0x119000 0x1000>;
102 reg = <0x11a000 0x1000>;
108 reg = <0x42000 0x1000>;
115 reg = <0x96000 0x1000>;
116 interrupts = <17 0>,<18 0>;
125 reg = <0x98000 0x1000>;
126 interrupts = <19 0>,<20 0>;
135 reg = <0x9a000 0x1000>;
136 interrupts = <21 0>,<22 0>;
145 reg = <0x9c000 0x1000>;
146 interrupts = <23 0>,<24 0>;
155 reg = <0x9e000 0x1000>;
156 interrupts = <25 0>,<26 0>;
165 reg = <0x40000 0x1000>;
166 interrupts = <27 0>,<28 0>;
174 reg = <0x92000 0x1000>;
175 interrupts = <35 0>;
184 reg = <0x92000 0x1000>;
190 reg = <0x92000 0x1000>;
193 #size-cells = <0>;
198 reg = <0x92800 0x1000>;
201 #size-cells = <0>;
208 reg = <0x93000 0x1000>;
209 interrupts = <36 0>;
218 reg = <0x93000 0x1000>;
220 /* DMA channels 0 and 1, muxed to LPUART1 RX and TX */
221 dmas = <&edma0 0 71>, <&edma0 1 72>;
227 reg = <0x93000 0x1000>;
230 #size-cells = <0>;
231 /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
232 dmas = <&edma0 0 71>, <&edma0 1 72>;
238 reg = <0x93800 0x1000>;
241 #size-cells = <0>;
248 reg = <0x94000 0x1000>;
249 interrupts = <37 0>;
258 reg = <0x94000 0x1000>;
267 reg = <0x94000 0x1000>;
270 #size-cells = <0>;
278 reg = <0x94800 0x1000>;
281 #size-cells = <0>;
288 reg = <0x95000 0x1000>;
289 interrupts = <38 0>;
298 reg = <0x95000 0x1000>;
304 reg = <0x95000 0x1000>;
307 #size-cells = <0>;
312 reg = <0x95800 0x1000>;
315 #size-cells = <0>;
322 reg = <0xb4000 0x1000>;
323 interrupts = <39 0>;
332 reg = <0xb4000 0x1000>;
341 reg = <0xb4000 0x1000>;
344 #size-cells = <0>;
352 reg = <0xb4800 0x1000>;
355 #size-cells = <0>;
362 reg = <0xb5000 0x1000>;
363 interrupts = <40 0>;
372 reg = <0xb5000 0x1000>;
378 reg = <0xb5000 0x1000>;
381 #size-cells = <0>;
386 reg = <0xb5800 0x1000>;
389 #size-cells = <0>;
396 reg = <0xb6000 0x1000>;
397 interrupts = <41 0>;
406 reg = <0xb6000 0x1000>;
412 reg = <0xb6000 0x1000>;
415 #size-cells = <0>;
420 reg = <0xb6800 0x1000>;
423 #size-cells = <0>;
430 reg = <0xb7000 0x1000>;
431 interrupts = <42 0>;
440 reg = <0xb7000 0x1000>;
446 reg = <0xb7000 0x1000>;
449 #size-cells = <0>;
454 reg = <0xb7800 0x1000>;
457 #size-cells = <0>;
469 reg = <0x80000 0x1000>;
470 interrupts = <1 0>, <2 0>, <3 0>, <4 0>,
471 <5 0>, <6 0>, <7 0>, <8 0>,
472 <9 0>, <10 0>, <11 0>, <12 0>,
473 <13 0>, <14 0>, <15 0>, <16 0>;
485 reg = <0xa0000 0x1000>;
486 interrupts = <77 0>, <78 0>, <79 0>, <80 0>,
487 <81 0>, <82 0>, <83 0>, <84 0>,
488 <85 0>, <86 0>, <87 0>, <88 0>,
489 <89 0>, <90 0>, <91 0>, <92 0>;
496 reg = <0x43000 0x1000>;
497 interrupts = <138 0>;
503 flash: flash@0 {
505 reg = <0 DT_SIZE_M(1)>;
514 reg = <0x49000 0x1000>;
515 interrupts = <57 0>;
521 reg = <0x16000 0x1000>;
522 interrupts = <152 0>;
529 reg = <0xce000 0x1000>;
531 interrupts = <112 0>, <113 0>;
534 index = <0>;
535 interrupts = <114 0>;
546 interrupts = <115 0>;
557 interrupts = <116 0>;
568 interrupts = <117 0>;
579 reg = <0xd0000 0x1000>;
581 interrupts = <118 0>, <119 0>;
584 index = <0>;
585 interrupts = <120 0>;
596 interrupts = <121 0>;
607 interrupts = <122 0>;
618 interrupts = <123 0>;
629 reg = <0xc000 0x1000>;
630 interrupts = <31 0>;
634 mode = <0>;
635 input = <0>;
636 prescale = <0>;
641 reg = <0xd000 0x1000>;
642 interrupts = <32 0>;
646 mode = <0>;
647 input = <0>;
648 prescale = <0>;
653 reg = <0xe000 0x1000>;
654 interrupts = <34 0>;
658 mode = <0>;
659 input = <0>;
660 prescale = <0>;
665 reg = <0xf000 0x1000>;
666 interrupts = <55 0>;
670 mode = <0>;
671 input = <0>;
672 prescale = <0>;
677 reg = <0x10000 0x1000>;
678 interrupts = <56 0>;
682 mode = <0>;
683 input = <0>;
684 prescale = <0>;
690 reg = <0x111000 0x14>;
701 reg = <0x10d000 0x1000>;
702 interrupts = <45 0>;
705 clk-source = <0>;
708 power-level = <0>;
709 offset-value-a = <0>;
710 offset-value-b = <0>;
718 reg = <0x10e000 0x1000>;
719 interrupts = <46 0>;
722 clk-source = <0>;
723 voltage-ref= <0>;
726 offset-value-a = <0>;
727 offset-value-b = <0>;
734 reg = <0x10b000 0x1000>;
735 interrupts = <67 0>;
743 reg = <0x51000 0x1000>;
744 interrupts = <109 0>;
751 reg = <0x52000 0x1000>;
752 interrupts = <110 0>;
759 reg = <0xd4000 0x4000>;
760 interrupts = <62 0>;
763 clk-source = <0>;
769 reg = <0xd8000 0x4000>;
770 interrupts = <63 0>;
773 clk-source = <0>;
779 reg = <0x105000 0x1000>;
781 interrupts = <105 0>;
791 reg = <0x4a000 0x1000>;
792 interrupts = <143 0>;
801 reg = <0x4b000 0x1000>;
802 interrupts = <144 0>;
811 reg = <0x13000 0x1000>;
812 interrupts = <30 0>;
816 resets = <&reset NXP_SYSCON_RESET(1, 0)>;
818 #size-cells = <0>;
820 mrt0_channel0: mrt0_channel@0 {
822 reg = <0>;
844 reg = <0x4c000 0x1000>;
846 interrupts = <52 0>;
849 clock-src = <0>;