1/*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <nordic/nrf_common.dtsi>
9#include <zephyr/dt-bindings/adc/nrf-saadc.h>
10#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
11#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
12#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
13#include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
14
15/delete-node/ &sw_pwm;
16
17/ {
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpuapp: cpu@2 {
26			compatible = "arm,cortex-m33";
27			reg = <2>;
28			device_type = "cpu";
29			clock-frequency = <DT_FREQ_M(320)>;
30		};
31
32		cpurad: cpu@3 {
33			compatible = "arm,cortex-m33";
34			reg = <3>;
35			device_type = "cpu";
36			clock-frequency = <DT_FREQ_M(256)>;
37		};
38
39		cpuppr: cpu@d {
40			compatible = "nordic,vpr";
41			reg = <13>;
42			device_type = "cpu";
43			clock-frequency = <DT_FREQ_M(16)>;
44			riscv,isa = "rv32emc";
45			nordic,bus-width = <32>;
46
47			cpuppr_vevif_rx: mailbox {
48				compatible = "nordic,nrf-vevif-task-rx";
49				status = "disabled";
50				interrupt-parent = <&cpuppr_clic>;
51				interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
52					     <1 NRF_DEFAULT_IRQ_PRIORITY>,
53					     <2 NRF_DEFAULT_IRQ_PRIORITY>,
54					     <3 NRF_DEFAULT_IRQ_PRIORITY>,
55					     <4 NRF_DEFAULT_IRQ_PRIORITY>,
56					     <5 NRF_DEFAULT_IRQ_PRIORITY>,
57					     <6 NRF_DEFAULT_IRQ_PRIORITY>,
58					     <7 NRF_DEFAULT_IRQ_PRIORITY>,
59					     <8 NRF_DEFAULT_IRQ_PRIORITY>,
60					     <9 NRF_DEFAULT_IRQ_PRIORITY>,
61					     <10 NRF_DEFAULT_IRQ_PRIORITY>,
62					     <11 NRF_DEFAULT_IRQ_PRIORITY>,
63					     <12 NRF_DEFAULT_IRQ_PRIORITY>,
64					     <13 NRF_DEFAULT_IRQ_PRIORITY>,
65					     <14 NRF_DEFAULT_IRQ_PRIORITY>,
66					     <15 NRF_DEFAULT_IRQ_PRIORITY>;
67				#mbox-cells = <1>;
68				nordic,tasks = <16>;
69				nordic,tasks-mask = <0x0000fff0>;
70			};
71		};
72	};
73
74	reserved-memory {
75		#address-cells = <1>;
76		#size-cells = <1>;
77
78		suit_storage_partition: memory@e6b7000 {
79			reg = <0xe6b7000 DT_SIZE_K(40)>;
80		};
81	};
82
83	clocks {
84		hfxo: hfxo {
85			compatible = "fixed-clock";
86			#clock-cells = <0>;
87			clock-frequency = <DT_FREQ_M(32)>;
88		};
89
90		fll16m: fll16m {
91			compatible = "fixed-clock";
92			#clock-cells = <0>;
93			clock-frequency = <DT_FREQ_M(16)>;
94		};
95	};
96
97	soc {
98		#address-cells = <1>;
99		#size-cells = <1>;
100
101		mram1x: mram@e000000 {
102			compatible = "nordic,mram";
103			reg = <0xe000000 DT_SIZE_K(8192)>;
104			erase-block-size = <4096>;
105			write-block-size = <16>;
106		};
107
108		cpuapp_uicr: uicr@fff8000 {
109			compatible = "nordic,nrf-uicr-v2";
110			reg = <0xfff8000 DT_SIZE_K(2)>;
111			domain = <2>;
112		};
113
114		cpurad_uicr: uicr@fffa000 {
115			compatible = "nordic,nrf-uicr-v2";
116			reg = <0xfffa000 DT_SIZE_K(2)>;
117			domain = <3>;
118		};
119
120		ficr: ficr@fffe000 {
121			compatible = "nordic,nrf-ficr";
122			reg = <0xfffe000 DT_SIZE_K(2)>;
123			#nordic,ficr-cells = <1>;
124		};
125
126		cpuapp_ram0: sram@22000000 {
127			compatible = "mmio-sram";
128			reg = <0x22000000 DT_SIZE_K(32)>;
129			#address-cells = <1>;
130			#size-cells = <1>;
131			ranges = <0x0 0x22000000 0x8000>;
132		};
133
134		cpurad_ram0: sram@23000000 {
135			compatible = "mmio-sram";
136			reg = <0x23000000 DT_SIZE_K(192)>;
137			#address-cells = <1>;
138			#size-cells = <1>;
139			ranges = <0x0 0x23000000 0x30000>;
140		};
141
142		cpurad_ram1: sram@23040000 {
143			compatible = "mmio-sram";
144			reg = <0x23040000 DT_SIZE_K(32)>;
145			#address-cells = <1>;
146			#size-cells = <1>;
147			ranges = <0x0 0x23040000 0x8000>;
148		};
149
150		cpuapp_peripherals: peripheral@52000000 {
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x0 0x52000000 0x1000000>;
154
155			cpuapp_hsfll: clock@d000 {
156				compatible = "nordic,nrf-hsfll-local";
157				#clock-cells = <0>;
158				reg = <0xd000 0x1000>;
159				clocks = <&fll16m>;
160				clock-frequency = <DT_FREQ_M(320)>;
161				nordic,ficrs =
162					<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>,
163					<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>,
164					<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>;
165				nordic,ficr-names = "vsup", "coarse", "fine";
166			};
167
168			cpuapp_ipct: ipct@13000 {
169				compatible = "nordic,nrf-ipct-local";
170				reg = <0x13000 0x1000>;
171				status = "disabled";
172				channels = <4>;
173				interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
174					     <65 NRF_DEFAULT_IRQ_PRIORITY>;
175			};
176
177			cpuapp_wdt010: watchdog@14000 {
178				compatible = "nordic,nrf-wdt";
179				reg = <0x14000 0x1000>;
180				status = "disabled";
181				interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
182			};
183
184			cpuapp_wdt011: watchdog@15000 {
185				compatible = "nordic,nrf-wdt";
186				reg = <0x15000 0x1000>;
187				status = "disabled";
188				interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>;
189			};
190
191			cpuapp_ieee802154: ieee802154 {
192				compatible = "nordic,nrf-ieee802154";
193				status = "disabled";
194			};
195
196			cpuapp_resetinfo: resetinfo@1e000 {
197				compatible = "nordic,nrf-resetinfo";
198				reg = <0x1e000 0x1000>;
199			};
200		};
201
202		cpurad_peripherals: peripheral@53000000 {
203			#address-cells = <1>;
204			#size-cells = <1>;
205			ranges = <0x0 0x53000000 0x1000000>;
206
207			cpurad_hsfll: clock@d000 {
208				compatible = "nordic,nrf-hsfll-local";
209				#clock-cells = <0>;
210				reg = <0xd000 0x1000>;
211				clocks = <&fll16m>;
212				clock-frequency = <DT_FREQ_M(256)>;
213				nordic,ficrs =
214					<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>,
215					<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>,
216					<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>;
217				nordic,ficr-names = "vsup", "coarse", "fine";
218			};
219
220			cpurad_wdt010: watchdog@13000 {
221				compatible = "nordic,nrf-wdt";
222				reg = <0x13000 0x1000>;
223				status = "disabled";
224				interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>;
225			};
226
227			cpurad_wdt011: watchdog@14000 {
228				compatible = "nordic,nrf-wdt";
229				reg = <0x14000 0x1000>;
230				status = "disabled";
231				interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
232			};
233
234			cpurad_resetinfo: resetinfo@1e000 {
235				compatible = "nordic,nrf-resetinfo";
236				reg = <0x1e000 0x1000>;
237			};
238
239			dppic020: dppic@22000 {
240				compatible = "nordic,nrf-dppic-local";
241				reg = <0x22000 0x1000>;
242				status = "disabled";
243			};
244
245			cpurad_ipct: ipct@24000 {
246				compatible = "nordic,nrf-ipct-local";
247				reg = <0x24000 0x1000>;
248				status = "disabled";
249				channels = <8>;
250				interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
251					     <65 NRF_DEFAULT_IRQ_PRIORITY>;
252			};
253
254			egu020: egu@25000 {
255				compatible = "nordic,nrf-egu";
256				reg = <0x25000 0x1000>;
257				status = "disabled";
258				interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>;
259			};
260
261			timer020: timer@28000 {
262				compatible = "nordic,nrf-timer";
263				reg = <0x28000 0x1000>;
264				status = "disabled";
265				cc-num = <8>;
266				interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>;
267				max-bit-width = <32>;
268				max-frequency = <DT_FREQ_M(32)>;
269				prescaler = <0>;
270			};
271
272			timer021: timer@29000 {
273				compatible = "nordic,nrf-timer";
274				reg = <0x29000 0x1000>;
275				status = "disabled";
276				cc-num = <8>;
277				interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>;
278				max-bit-width = <32>;
279				max-frequency = <DT_FREQ_M(32)>;
280				prescaler = <0>;
281			};
282
283			timer022: timer@2a000 {
284				compatible = "nordic,nrf-timer";
285				reg = <0x2a000 0x1000>;
286				status = "disabled";
287				cc-num = <8>;
288				interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>;
289				max-bit-width = <32>;
290				max-frequency = <DT_FREQ_M(32)>;
291				prescaler = <0>;
292			};
293
294			rtc: rtc@2b000 {
295				compatible = "nordic,nrf-rtc";
296				reg = <0x2b000 0x1000>;
297				status = "disabled";
298				cc-num = <4>;
299				clock-frequency = <32768>;
300				interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>;
301				prescaler = <1>;
302			};
303
304			radio: radio@2c000 {
305				compatible = "nordic,nrf-radio";
306				reg = <0x2c000 0x1000>;
307				status = "disabled";
308				ble-2mbps-supported;
309				ble-coded-phy-supported;
310				dfe-supported;
311				ieee802154-supported;
312				interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>;
313
314				cpurad_ieee802154: ieee802154 {
315					compatible = "nordic,nrf-ieee802154";
316					status = "disabled";
317				};
318			};
319
320			ccm030: ccm@3a000 {
321				compatible = "nordic,nrf-ccm";
322				reg = <0x3a000 0x1000>;
323				interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>;
324				status = "disabled";
325			};
326
327			ecb030: ecb@3b000 {
328				compatible = "nordic,nrf-ecb";
329				reg = <0x3b000 0x1000>;
330				interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>;
331				status = "disabled";
332			};
333
334			ccm031: ccm@3c000 {
335				compatible = "nordic,nrf-ccm";
336				reg = <0x3c000 0x1000>;
337				interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>;
338				status = "disabled";
339			};
340
341			ecb031: ecb@3d000 {
342				compatible = "nordic,nrf-ecb";
343				reg = <0x3d000 0x1000>;
344				status = "disabled";
345				interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>;
346			};
347		};
348
349		global_peripherals: peripheral@5f000000 {
350			#address-cells = <1>;
351			#size-cells = <1>;
352			ranges = <0x0 0x5f000000 0x1000000>;
353
354			usbhs: usbhs@86000 {
355				compatible = "nordic,nrf-usbhs", "snps,dwc2";
356				reg = <0x86000 0x1000>, <0x2f700000 0x40000>;
357				reg-names = "wrapper", "core";
358				interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>;
359				num-in-eps = <8>;
360				num-out-eps = <10>;
361				ghwcfg1 = <0xaa555000>;
362				ghwcfg2 = <0x22abfc72>;
363				ghwcfg4 = <0x1e10aa60>;
364				status = "disabled";
365			};
366
367			exmif: spi@95000 {
368				compatible = "nordic,nrf-exmif";
369				#address-cells = <1>;
370				#size-cells = <0>;
371				reg = <0x95000 0x500 0x95500 0xb00>;
372				reg-names = "wrapper", "core";
373				interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>;
374				clock-frequency = <DT_FREQ_M(400)>;
375				fifo-depth = <32>;
376				max-xfer-size = <16>;
377				status = "disabled";
378			};
379
380			cpusec_bellboard: mailbox@99000 {
381				reg = <0x99000 0x1000>;
382				status = "disabled";
383				#mbox-cells = <1>;
384			};
385
386			cpuapp_bellboard: mailbox@9a000 {
387				reg = <0x9a000 0x1000>;
388				status = "disabled";
389				#mbox-cells = <1>;
390			};
391
392			cpurad_bellboard: mailbox@9b000 {
393				reg = <0x9b000 0x1000>;
394				status = "disabled";
395				#mbox-cells = <1>;
396			};
397
398			cpucell_bellboard: mailbox@9c000 {
399				reg = <0x9c000 0x1000>;
400				status = "disabled";
401				#mbox-cells = <1>;
402			};
403
404			canpll: clock-controller@8c2000{
405				compatible = "nordic,nrf-auxpll";
406				reg = <0x8c2000 0x1000>;
407				interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>;
408				clocks = <&hfxo>;
409				#clock-cells = <0>;
410				nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>;
411				nordic,frequency = <0>;
412				nordic,out-div = <2>;
413				nordic,out-drive = <0>;
414				nordic,current-tune = <6>;
415				nordic,sdm-disable;
416				nordic,range = "high";
417				status = "disabled";
418			};
419
420			cpusys_vevif_tx: mailbox@8c8000 {
421				compatible = "nordic,nrf-vevif-task-tx";
422				reg = <0x8c8000 0x1000>;
423				status = "disabled";
424				#mbox-cells = <1>;
425				nordic,tasks = <32>;
426				nordic,tasks-mask = <0xfffff0ff>;
427			};
428
429			ipct120: ipct@8d1000 {
430				compatible = "nordic,nrf-ipct-global";
431				reg = <0x8d1000 0x1000>;
432				status = "disabled";
433				channels = <8>;
434				global-domain-id = <12>;
435			};
436
437			can120: can@8d8000 {
438				compatible = "nordic,nrf-can";
439				reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
440				reg-names = "wrapper", "m_can", "message_ram";
441				interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>;
442				clocks = <&canpll>;
443				bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
444				status = "disabled";
445			};
446
447			can121: can@8db000 {
448				compatible = "nordic,nrf-can";
449				reg = <0x8db000 0x400>, <0x2fbf7800 0x800>, <0x2fbf0000 0x7800>;
450				reg-names = "wrapper", "m_can", "message_ram";
451				interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
452				clocks = <&canpll>;
453				bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
454				status = "disabled";
455			};
456
457			dppic120: dppic@8e1000 {
458				compatible = "nordic,nrf-dppic-global";
459				reg = <0x8e1000 0x1000>;
460				status = "disabled";
461			};
462
463			timer120: timer@8e2000 {
464				compatible = "nordic,nrf-timer";
465				reg = <0x8e2000 0x1000>;
466				status = "disabled";
467				cc-num = <6>;
468				interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
469				max-bit-width = <32>;
470				max-frequency = <DT_FREQ_M(320)>;
471				prescaler = <0>;
472			};
473
474			timer121: timer@8e3000 {
475				compatible = "nordic,nrf-timer";
476				reg = <0x8e3000 0x1000>;
477				status = "disabled";
478				cc-num = <6>;
479				interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>;
480				max-bit-width = <32>;
481				max-frequency = <DT_FREQ_M(320)>;
482				prescaler = <0>;
483			};
484
485			pwm120: pwm@8e4000 {
486				compatible = "nordic,nrf-pwm";
487				reg = <0x8e4000 0x1000>;
488				status = "disabled";
489				interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>;
490				#pwm-cells = <3>;
491			};
492
493			spi120: spi@8e6000 {
494				compatible = "nordic,nrf-spim";
495				reg = <0x8e6000 0x1000>;
496				status = "disabled";
497				easydma-maxcnt-bits = <15>;
498				interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
499				max-frequency = <DT_FREQ_M(32)>;
500				#address-cells = <1>;
501				#size-cells = <0>;
502				rx-delay-supported;
503				rx-delay = <1>;
504				nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
505							 <NRF_FUN_SPIS_SCK>;
506			};
507
508			uart120: uart@8e6000 {
509				compatible = "nordic,nrf-uarte";
510				reg = <0x8e6000 0x1000>;
511				status = "disabled";
512				interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
513				endtx-stoptx-supported;
514				frame-timeout-supported;
515			};
516
517			spi121: spi@8e7000 {
518				compatible = "nordic,nrf-spim";
519				reg = <0x8e7000 0x1000>;
520				status = "disabled";
521				easydma-maxcnt-bits = <15>;
522				interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>;
523				max-frequency = <DT_FREQ_M(32)>;
524				#address-cells = <1>;
525				#size-cells = <0>;
526				rx-delay-supported;
527				rx-delay = <1>;
528				nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
529							 <NRF_FUN_SPIS_SCK>;
530			};
531
532			cpuppr_vpr: vpr@908000 {
533				compatible = "nordic,nrf-vpr-coprocessor";
534				reg = <0x908000 0x1000>;
535				status = "disabled";
536				#address-cells = <1>;
537				#size-cells = <1>;
538				ranges = <0x0 0x908000 0x1000>;
539
540				cpuppr_vevif_tx: mailbox@0 {
541					compatible = "nordic,nrf-vevif-task-tx";
542					reg = <0x0 0x1000>;
543					status = "disabled";
544					#mbox-cells = <1>;
545					nordic,tasks = <16>;
546					nordic,tasks-mask = <0x0000fff0>;
547				};
548			};
549
550			ipct130: ipct@921000 {
551				compatible = "nordic,nrf-ipct-global";
552				reg = <0x921000 0x1000>;
553				status = "disabled";
554				channels = <8>;
555				global-domain-id = <13>;
556			};
557
558			dppic130: dppic@922000 {
559				compatible = "nordic,nrf-dppic-global";
560				reg = <0x922000 0x1000>;
561				status = "disabled";
562			};
563
564			rtc130: rtc@928000 {
565				compatible = "nordic,nrf-rtc";
566				reg = <0x928000 0x1000>;
567				status = "disabled";
568				cc-num = <4>;
569				clock-frequency = <32768>;
570				interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>;
571				prescaler = <1>;
572			};
573
574			rtc131: rtc@929000 {
575				compatible = "nordic,nrf-rtc";
576				reg = <0x929000 0x1000>;
577				status = "disabled";
578				cc-num = <4>;
579				clock-frequency = <32768>;
580				interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>;
581				prescaler = <1>;
582			};
583
584			wdt131: watchdog@92b000 {
585				compatible = "nordic,nrf-wdt";
586				reg = <0x92b000 0x1000>;
587				status = "disabled";
588				interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>;
589			};
590
591			wdt132: watchdog@92c000 {
592				compatible = "nordic,nrf-wdt";
593				reg = <0x92c000 0x1000>;
594				status = "disabled";
595				interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>;
596			};
597
598			gpiote130: gpiote@934000 {
599				compatible = "nordic,nrf-gpiote";
600				reg = <0x934000 0x1000>;
601				status = "disabled";
602				instance = <130>;
603			};
604
605			gpiote131: gpiote@935000 {
606				compatible = "nordic,nrf-gpiote";
607				reg = <0x935000 0x1000>;
608				status = "disabled";
609				instance = <131>;
610			};
611
612			gpio0: gpio@938000 {
613				compatible = "nordic,nrf-gpio";
614				reg = <0x938000 0x200>;
615				status = "disabled";
616				#gpio-cells = <2>;
617				gpio-controller;
618				gpiote-instance = <&gpiote130>;
619				ngpios = <13>;
620				port = <0>;
621			};
622
623			gpio1: gpio@938200 {
624				compatible = "nordic,nrf-gpio";
625				reg = <0x938200 0x200>;
626				status = "disabled";
627				#gpio-cells = <2>;
628				gpio-controller;
629				gpiote-instance = <&gpiote130>;
630				ngpios = <12>;
631				port = <1>;
632			};
633
634			gpio2: gpio@938400 {
635				compatible = "nordic,nrf-gpio";
636				reg = <0x938400 0x200>;
637				status = "disabled";
638				#gpio-cells = <2>;
639				gpio-controller;
640				gpiote-instance = <&gpiote130>;
641				ngpios = <12>;
642				port = <2>;
643			};
644
645			gpio6: gpio@938c00 {
646				compatible = "nordic,nrf-gpio";
647				reg = <0x938c00 0x200>;
648				status = "disabled";
649				#gpio-cells = <2>;
650				gpio-controller;
651				ngpios = <14>;
652				port = <6>;
653			};
654
655			gpio8: gpio@939000 {
656				compatible = "nordic,nrf-gpio";
657				reg = <0x939000 0x200>;
658				status = "disabled";
659				#gpio-cells = <2>;
660				gpio-controller;
661				ngpios = <5>;
662				port = <8>;
663			};
664
665			gpio9: gpio@939200 {
666				compatible = "nordic,nrf-gpio";
667				reg = <0x939200 0x200>;
668				status = "disabled";
669				#gpio-cells = <2>;
670				gpio-controller;
671				gpiote-instance = <&gpiote130>;
672				ngpios = <6>;
673				port = <9>;
674			};
675
676			gpio11: gpio@939600 {
677				compatible = "nordic,nrf-gpio";
678				reg = <0x939600 0x200>;
679				status = "disabled";
680				#gpio-cells = <2>;
681				gpio-controller;
682				gpiote-instance = <&gpiote131>;
683				ngpios = <8>;
684				port = <11>;
685			};
686
687			dppic131: dppic@981000 {
688				compatible = "nordic,nrf-dppic-global";
689				reg = <0x981000 0x1000>;
690				status = "disabled";
691			};
692
693			adc: adc@982000 {
694				compatible = "nordic,nrf-saadc";
695				reg = <0x982000 0x1000>;
696				interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>;
697				status = "disabled";
698				#io-channel-cells = <1>;
699			};
700
701			comp: comparator@983000 {
702				/*
703				 * Use compatible "nordic,nrf-comp" to configure as COMP
704				 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
705				 */
706				compatible = "nordic,nrf-comp";
707				reg = <0x983000 0x1000>;
708				status = "disabled";
709				interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>;
710			};
711
712			temp: temperature-sensor@984000 {
713				compatible = "nordic,nrf-temp";
714				reg = <0x984000 0x1000>;
715				interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>;
716				status = "disabled";
717			};
718
719			dppic132: dppic@991000 {
720				compatible = "nordic,nrf-dppic-global";
721				reg = <0x991000 0x1000>;
722				status = "disabled";
723			};
724
725			qdec130: qdec@994000 {
726				compatible = "nordic,nrf-qdec";
727				reg = <0x994000 0x1000>;
728				status = "disabled";
729				interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>;
730			};
731
732			qdec131: qdec@995000 {
733				compatible = "nordic,nrf-qdec";
734				reg = <0x995000 0x1000>;
735				status = "disabled";
736				interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>;
737			};
738
739			grtc: grtc@99c000 {
740				compatible = "nordic,nrf-grtc";
741				reg = <0x99c000 0x1000>;
742				status = "disabled";
743				cc-num = <16>;
744			};
745
746			dppic133: dppic@9a1000 {
747				compatible = "nordic,nrf-dppic-global";
748				reg = <0x9a1000 0x1000>;
749				status = "disabled";
750			};
751
752			timer130: timer@9a2000 {
753				compatible = "nordic,nrf-timer";
754				reg = <0x9a2000 0x1000>;
755				status = "disabled";
756				cc-num = <6>;
757				interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>;
758				max-bit-width = <32>;
759				prescaler = <0>;
760			};
761
762			timer131: timer@9a3000 {
763				compatible = "nordic,nrf-timer";
764				reg = <0x9a3000 0x1000>;
765				status = "disabled";
766				cc-num = <6>;
767				interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>;
768				max-bit-width = <32>;
769				prescaler = <0>;
770			};
771
772			pwm130: pwm@9a4000 {
773				compatible = "nordic,nrf-pwm";
774				reg = <0x9a4000 0x1000>;
775				status = "disabled";
776				interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>;
777				#pwm-cells = <3>;
778			};
779
780			i2c130: i2c@9a5000 {
781				compatible = "nordic,nrf-twim";
782				reg = <0x9a5000 0x1000>;
783				status = "disabled";
784				interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
785				easydma-maxcnt-bits = <15>;
786				#address-cells = <1>;
787				#size-cells = <0>;
788				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
789							 <NRF_FUN_TWIM_SCL>;
790				zephyr,pm-device-runtime-auto;
791			};
792
793			spi130: spi@9a5000 {
794				compatible = "nordic,nrf-spim";
795				reg = <0x9a5000 0x1000>;
796				status = "disabled";
797				easydma-maxcnt-bits = <15>;
798				interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
799				max-frequency = <DT_FREQ_M(8)>;
800				#address-cells = <1>;
801				#size-cells = <0>;
802				rx-delay-supported;
803				rx-delay = <1>;
804				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
805							 <NRF_FUN_SPIM_SCK>,
806							 <NRF_FUN_SPIS_MISO>,
807							 <NRF_FUN_SPIS_SCK>;
808			};
809
810			uart130: uart@9a5000 {
811				compatible = "nordic,nrf-uarte";
812				reg = <0x9a5000 0x1000>;
813				status = "disabled";
814				interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
815				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
816				endtx-stoptx-supported;
817				frame-timeout-supported;
818			};
819
820			i2c131: i2c@9a6000 {
821				compatible = "nordic,nrf-twim";
822				reg = <0x9a6000 0x1000>;
823				status = "disabled";
824				interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
825				easydma-maxcnt-bits = <15>;
826				#address-cells = <1>;
827				#size-cells = <0>;
828				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
829							 <NRF_FUN_TWIM_SCL>;
830				zephyr,pm-device-runtime-auto;
831			};
832
833			spi131: spi@9a6000 {
834				compatible = "nordic,nrf-spim";
835				reg = <0x9a6000 0x1000>;
836				status = "disabled";
837				easydma-maxcnt-bits = <15>;
838				interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
839				max-frequency = <DT_FREQ_M(8)>;
840				#address-cells = <1>;
841				#size-cells = <0>;
842				rx-delay-supported;
843				rx-delay = <1>;
844				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
845							 <NRF_FUN_SPIM_SCK>,
846							 <NRF_FUN_SPIS_MISO>,
847							 <NRF_FUN_SPIS_SCK>;
848			};
849
850			uart131: uart@9a6000 {
851				compatible = "nordic,nrf-uarte";
852				reg = <0x9a6000 0x1000>;
853				status = "disabled";
854				interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
855				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
856				endtx-stoptx-supported;
857				frame-timeout-supported;
858			};
859
860			dppic134: dppic@9b1000 {
861				compatible = "nordic,nrf-dppic-global";
862				reg = <0x9b1000 0x1000>;
863				status = "disabled";
864			};
865
866			timer132: timer@9b2000 {
867				compatible = "nordic,nrf-timer";
868				reg = <0x9b2000 0x1000>;
869				status = "disabled";
870				cc-num = <6>;
871				interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>;
872				max-bit-width = <32>;
873				prescaler = <0>;
874			};
875
876			timer133: timer@9b3000 {
877				compatible = "nordic,nrf-timer";
878				reg = <0x9b3000 0x1000>;
879				status = "disabled";
880				cc-num = <6>;
881				interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>;
882				max-bit-width = <32>;
883				prescaler = <0>;
884			};
885
886			pwm131: pwm@9b4000 {
887				compatible = "nordic,nrf-pwm";
888				reg = <0x9b4000 0x1000>;
889				status = "disabled";
890				interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>;
891				#pwm-cells = <3>;
892			};
893
894			i2c132: i2c@9b5000 {
895				compatible = "nordic,nrf-twim";
896				reg = <0x9b5000 0x1000>;
897				status = "disabled";
898				interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
899				easydma-maxcnt-bits = <15>;
900				#address-cells = <1>;
901				#size-cells = <0>;
902				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
903							 <NRF_FUN_TWIM_SCL>;
904				zephyr,pm-device-runtime-auto;
905			};
906
907			spi132: spi@9b5000 {
908				compatible = "nordic,nrf-spim";
909				reg = <0x9b5000 0x1000>;
910				status = "disabled";
911				easydma-maxcnt-bits = <15>;
912				interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
913				max-frequency = <DT_FREQ_M(8)>;
914				#address-cells = <1>;
915				#size-cells = <0>;
916				rx-delay-supported;
917				rx-delay = <1>;
918				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
919							 <NRF_FUN_SPIM_SCK>,
920							 <NRF_FUN_SPIS_MISO>,
921							 <NRF_FUN_SPIS_SCK>;
922			};
923
924			uart132: uart@9b5000 {
925				compatible = "nordic,nrf-uarte";
926				reg = <0x9b5000 0x1000>;
927				status = "disabled";
928				interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
929				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
930				endtx-stoptx-supported;
931				frame-timeout-supported;
932			};
933
934			i2c133: i2c@9b6000 {
935				compatible = "nordic,nrf-twim";
936				reg = <0x9b6000 0x1000>;
937				status = "disabled";
938				interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
939				easydma-maxcnt-bits = <15>;
940				#address-cells = <1>;
941				#size-cells = <0>;
942				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
943							 <NRF_FUN_TWIM_SCL>;
944				zephyr,pm-device-runtime-auto;
945			};
946
947			spi133: spi@9b6000 {
948				compatible = "nordic,nrf-spim";
949				reg = <0x9b6000 0x1000>;
950				status = "disabled";
951				easydma-maxcnt-bits = <15>;
952				interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
953				max-frequency = <DT_FREQ_M(8)>;
954				#address-cells = <1>;
955				#size-cells = <0>;
956				rx-delay-supported;
957				rx-delay = <1>;
958				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
959							 <NRF_FUN_SPIM_SCK>,
960							 <NRF_FUN_SPIS_MISO>,
961							 <NRF_FUN_SPIS_SCK>;
962			};
963
964			uart133: uart@9b6000 {
965				compatible = "nordic,nrf-uarte";
966				reg = <0x9b6000 0x1000>;
967				status = "disabled";
968				interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
969				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
970				endtx-stoptx-supported;
971				frame-timeout-supported;
972			};
973
974			dppic135: dppic@9c1000 {
975				compatible = "nordic,nrf-dppic-global";
976				reg = <0x9c1000 0x1000>;
977				status = "disabled";
978			};
979
980			timer134: timer@9c2000 {
981				compatible = "nordic,nrf-timer";
982				reg = <0x9c2000 0x1000>;
983				status = "disabled";
984				cc-num = <6>;
985				interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>;
986				max-bit-width = <32>;
987				prescaler = <0>;
988			};
989
990			timer135: timer@9c3000 {
991				compatible = "nordic,nrf-timer";
992				reg = <0x9c3000 0x1000>;
993				status = "disabled";
994				cc-num = <6>;
995				interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>;
996				max-bit-width = <32>;
997				prescaler = <0>;
998			};
999
1000			pwm132: pwm@9c4000 {
1001				compatible = "nordic,nrf-pwm";
1002				reg = <0x9c4000 0x1000>;
1003				status = "disabled";
1004				interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>;
1005				#pwm-cells = <3>;
1006			};
1007
1008			i2c134: i2c@9c5000 {
1009				compatible = "nordic,nrf-twim";
1010				reg = <0x9c5000 0x1000>;
1011				status = "disabled";
1012				interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
1013				easydma-maxcnt-bits = <15>;
1014				#address-cells = <1>;
1015				#size-cells = <0>;
1016				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1017							 <NRF_FUN_TWIM_SCL>;
1018				zephyr,pm-device-runtime-auto;
1019			};
1020
1021			spi134: spi@9c5000 {
1022				compatible = "nordic,nrf-spim";
1023				reg = <0x9c5000 0x1000>;
1024				status = "disabled";
1025				easydma-maxcnt-bits = <15>;
1026				interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
1027				max-frequency = <DT_FREQ_M(8)>;
1028				#address-cells = <1>;
1029				#size-cells = <0>;
1030				rx-delay-supported;
1031				rx-delay = <1>;
1032				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1033							 <NRF_FUN_SPIM_SCK>,
1034							 <NRF_FUN_SPIS_MISO>,
1035							 <NRF_FUN_SPIS_SCK>;
1036			};
1037
1038			uart134: uart@9c5000 {
1039				compatible = "nordic,nrf-uarte";
1040				reg = <0x9c5000 0x1000>;
1041				status = "disabled";
1042				interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
1043				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1044				endtx-stoptx-supported;
1045				frame-timeout-supported;
1046			};
1047
1048			i2c135: i2c@9c6000 {
1049				compatible = "nordic,nrf-twim";
1050				reg = <0x9c6000 0x1000>;
1051				status = "disabled";
1052				interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
1053				easydma-maxcnt-bits = <15>;
1054				#address-cells = <1>;
1055				#size-cells = <0>;
1056				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1057							 <NRF_FUN_TWIM_SCL>;
1058				zephyr,pm-device-runtime-auto;
1059			};
1060
1061			spi135: spi@9c6000 {
1062				compatible = "nordic,nrf-spim";
1063				reg = <0x9c6000 0x1000>;
1064				status = "disabled";
1065				easydma-maxcnt-bits = <15>;
1066				interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
1067				max-frequency = <DT_FREQ_M(8)>;
1068				#address-cells = <1>;
1069				#size-cells = <0>;
1070				rx-delay-supported;
1071				rx-delay = <1>;
1072				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1073							 <NRF_FUN_SPIM_SCK>,
1074							 <NRF_FUN_SPIS_MISO>,
1075							 <NRF_FUN_SPIS_SCK>;
1076			};
1077
1078			uart135: uart@9c6000 {
1079				compatible = "nordic,nrf-uarte";
1080				reg = <0x9c6000 0x1000>;
1081				status = "disabled";
1082				interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
1083				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1084				endtx-stoptx-supported;
1085				frame-timeout-supported;
1086			};
1087
1088			dppic136: dppic@9d1000 {
1089				compatible = "nordic,nrf-dppic-global";
1090				reg = <0x9d1000 0x1000>;
1091				status = "disabled";
1092			};
1093
1094			timer136: timer@9d2000 {
1095				compatible = "nordic,nrf-timer";
1096				reg = <0x9d2000 0x1000>;
1097				status = "disabled";
1098				cc-num = <6>;
1099				interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>;
1100				max-bit-width = <32>;
1101				prescaler = <0>;
1102			};
1103
1104			timer137: timer@9d3000 {
1105				compatible = "nordic,nrf-timer";
1106				reg = <0x9d3000 0x1000>;
1107				status = "disabled";
1108				cc-num = <6>;
1109				interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>;
1110				max-bit-width = <32>;
1111				prescaler = <0>;
1112			};
1113
1114			pwm133: pwm@9d4000 {
1115				compatible = "nordic,nrf-pwm";
1116				reg = <0x9d4000 0x1000>;
1117				status = "disabled";
1118				interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>;
1119				#pwm-cells = <3>;
1120			};
1121
1122			i2c136: i2c@9d5000 {
1123				compatible = "nordic,nrf-twim";
1124				reg = <0x9d5000 0x1000>;
1125				status = "disabled";
1126				interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
1127				easydma-maxcnt-bits = <15>;
1128				#address-cells = <1>;
1129				#size-cells = <0>;
1130				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1131							 <NRF_FUN_TWIM_SCL>;
1132				zephyr,pm-device-runtime-auto;
1133			};
1134
1135			spi136: spi@9d5000 {
1136				compatible = "nordic,nrf-spim";
1137				reg = <0x9d5000 0x1000>;
1138				status = "disabled";
1139				easydma-maxcnt-bits = <15>;
1140				interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
1141				max-frequency = <DT_FREQ_M(8)>;
1142				#address-cells = <1>;
1143				#size-cells = <0>;
1144				rx-delay-supported;
1145				rx-delay = <1>;
1146				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1147							 <NRF_FUN_SPIM_SCK>,
1148							 <NRF_FUN_SPIS_MISO>,
1149							 <NRF_FUN_SPIS_SCK>;
1150			};
1151
1152			uart136: uart@9d5000 {
1153				compatible = "nordic,nrf-uarte";
1154				reg = <0x9d5000 0x1000>;
1155				status = "disabled";
1156				interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
1157				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1158				endtx-stoptx-supported;
1159				frame-timeout-supported;
1160			};
1161
1162			i2c137: i2c@9d6000 {
1163				compatible = "nordic,nrf-twim";
1164				reg = <0x9d6000 0x1000>;
1165				status = "disabled";
1166				interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
1167				easydma-maxcnt-bits = <15>;
1168				#address-cells = <1>;
1169				#size-cells = <0>;
1170				nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
1171							 <NRF_FUN_TWIM_SCL>;
1172				zephyr,pm-device-runtime-auto;
1173			};
1174
1175			spi137: spi@9d6000 {
1176				compatible = "nordic,nrf-spim";
1177				reg = <0x9d6000 0x1000>;
1178				status = "disabled";
1179				easydma-maxcnt-bits = <15>;
1180				interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
1181				max-frequency = <DT_FREQ_M(8)>;
1182				#address-cells = <1>;
1183				#size-cells = <0>;
1184				rx-delay-supported;
1185				rx-delay = <1>;
1186				nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
1187							 <NRF_FUN_SPIM_SCK>,
1188							 <NRF_FUN_SPIS_MISO>,
1189							 <NRF_FUN_SPIS_SCK>;
1190			};
1191
1192			uart137: uart@9d6000 {
1193				compatible = "nordic,nrf-uarte";
1194				reg = <0x9d6000 0x1000>;
1195				status = "disabled";
1196				interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
1197				nordic,clockpin-enable = <NRF_FUN_UART_TX>;
1198				endtx-stoptx-supported;
1199				frame-timeout-supported;
1200			};
1201		};
1202	};
1203
1204	cpuapp_ppb: cpuapp-ppb-bus {
1205		#address-cells = <1>;
1206		#size-cells = <1>;
1207
1208		cpuapp_systick: timer@e000e010 {
1209			compatible = "arm,armv8m-systick";
1210			reg = <0xe000e010 0x10>;
1211			status = "disabled";
1212		};
1213
1214		cpuapp_nvic: interrupt-controller@e000e100 {
1215			compatible = "arm,v8m-nvic";
1216			reg = <0xe000e100 0xc00>;
1217			arm,num-irq-priority-bits = <3>;
1218			#interrupt-cells = <2>;
1219			interrupt-controller;
1220			#address-cells = <1>;
1221		};
1222	};
1223
1224	cpurad_ppb: cpurad-ppb-bus {
1225		#address-cells = <1>;
1226		#size-cells = <1>;
1227
1228		cpurad_systick: timer@e000e010 {
1229			compatible = "arm,armv8m-systick";
1230			reg = <0xe000e010 0x10>;
1231			status = "disabled";
1232		};
1233
1234		cpurad_nvic: interrupt-controller@e000e100 {
1235			compatible = "arm,v8m-nvic";
1236			reg = <0xe000e100 0xc00>;
1237			arm,num-irq-priority-bits = <3>;
1238			#interrupt-cells = <2>;
1239			interrupt-controller;
1240			#address-cells = <1>;
1241		};
1242	};
1243
1244	cpuppr_private: cpuppr-private-bus {
1245		#address-cells = <1>;
1246		#size-cells = <1>;
1247
1248		cpuppr_clic: interrupt-controller@5f909000 {
1249			compatible = "nordic,nrf-clic";
1250			reg = <0x5f909000 0x3000>;
1251			status = "disabled";
1252			#interrupt-cells = <2>;
1253			interrupt-controller;
1254			#address-cells = <1>;
1255		};
1256	};
1257
1258	temp_nrfs: temp {
1259		compatible = "nordic,nrf-temp-nrfs";
1260		status = "disabled";
1261	};
1262};
1263