Lines Matching +full:0 +full:x1000
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe0000000 0x1000>;
37 reg = <0x10000000 0x1000>;
44 reg = <0x10001000 0x1000>;
54 reg = <0x40000000 0x1000>;
55 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
61 reg = <0x40000000 0x1000>;
62 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
71 reg = <0x4000051c 0x1>;
79 reg = <0x40000520 0x1>;
85 reg = <0x40000578 0x1>;
93 reg = <0x40000000 0x1000>;
99 reg = <0x40001000 0x1000>;
117 reg = <0x40002000 0x1000>;
132 #size-cells = <0>;
133 reg = <0x40003000 0x1000>;
150 #size-cells = <0>;
151 reg = <0x40004000 0x1000>;
160 reg = <0x40006000 0x1000>;
163 instance = <0>;
168 reg = <0x40007000 0x1000>;
176 reg = <0x40008000 0x1000>;
180 prescaler = <0>;
186 reg = <0x40009000 0x1000>;
190 prescaler = <0>;
196 reg = <0x4000a000 0x1000>;
200 prescaler = <0>;
205 reg = <0x4000b000 0x1000>;
215 reg = <0x4000c000 0x1000>;
222 reg = <0x4000d000 0x1000>;
229 reg = <0x4000e000 0x1000>;
236 reg = <0x4000f000 0x1000>;
244 reg = <0x40010000 0x1000>;
251 reg = <0x40011000 0x1000>;
261 reg = <0x40012000 0x1000>;
268 reg = <0x40013000 0x1000>;
275 reg = <0x40014000 0x1000>;
282 reg = <0x40015000 0x1000>;
289 reg = <0x40016000 0x1000>;
296 reg = <0x40017000 0x1000>;
303 reg = <0x40018000 0x1000>;
310 reg = <0x40019000 0x1000>;
317 reg = <0x4001c000 0x1000>;
325 reg = <0x4001d000 0x1000>;
332 reg = <0x4001e000 0x1000>;
339 flash0: flash@0 {
348 reg = <0x4001f000 0x1000>;
355 reg = <0x50000000 0x1000>;
358 port = <0>;