Lines Matching +full:0 +full:x1000
21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
75 reg = <0x4000051c 0x1>;
83 reg = <0x40000520 0x1>;
89 reg = <0x40000578 0x1>;
97 reg = <0x40000000 0x1000>;
103 reg = <0x40001000 0x1000>;
129 reg = <0x40002000 0x1000>;
144 #size-cells = <0>;
145 reg = <0x40003000 0x1000>;
163 #size-cells = <0>;
164 reg = <0x40003000 0x1000>;
181 #size-cells = <0>;
182 reg = <0x40004000 0x1000>;
191 reg = <0x40006000 0x1000>;
194 instance = <0>;
199 reg = <0x40007000 0x1000>;
208 reg = <0x40008000 0x1000>;
212 prescaler = <0>;
218 reg = <0x40009000 0x1000>;
222 prescaler = <0>;
228 reg = <0x4000a000 0x1000>;
232 prescaler = <0>;
237 reg = <0x4000b000 0x1000>;
247 reg = <0x4000c000 0x1000>;
254 reg = <0x4000d000 0x1000>;
261 reg = <0x4000e000 0x1000>;
268 reg = <0x4000f000 0x1000>;
276 reg = <0x40010000 0x1000>;
283 reg = <0x40011000 0x1000>;
293 reg = <0x40012000 0x1000>;
300 reg = <0x40013000 0x1000>;
307 reg = <0x40014000 0x1000>;
314 reg = <0x40015000 0x1000>;
321 reg = <0x40016000 0x1000>;
328 reg = <0x40017000 0x1000>;
335 reg = <0x40018000 0x1000>;
342 reg = <0x40019000 0x1000>;
349 reg = <0x4001c000 0x1000>;
357 reg = <0x4001d000 0x1000>;
364 reg = <0x4001e000 0x1000>;
371 flash0: flash@0 {
380 reg = <0x4001f000 0x1000>;
389 reg = <0x50000000 0x200
390 0x50000500 0x300>;
393 port = <0>;