1/* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <nordic/nrf_common.dtsi> 9 10#include <zephyr/dt-bindings/adc/nrf-saadc.h> 11#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h> 12#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h> 13#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h> 14#include <zephyr/dt-bindings/misc/nordic-tddconf.h> 15#include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h> 16#include <zephyr/dt-bindings/power/nordic-nrf-gpd.h> 17 18/delete-node/ &sw_pwm; 19 20/ { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpuapp: cpu@2 { 29 compatible = "arm,cortex-m33"; 30 reg = <2>; 31 device_type = "cpu"; 32 clocks = <&cpuapp_hsfll>; 33 clock-frequency = <DT_FREQ_M(320)>; 34 cpu-power-states = <&idle_cache_disabled &s2ram>; 35 }; 36 37 cpurad: cpu@3 { 38 compatible = "arm,cortex-m33"; 39 reg = <3>; 40 device_type = "cpu"; 41 clocks = <&cpurad_hsfll>; 42 clock-frequency = <DT_FREQ_M(256)>; 43 cpu-power-states = <&idle_cache_disabled>; 44 }; 45 46 cpuppr: cpu@d { 47 compatible = "nordic,vpr"; 48 reg = <13>; 49 device_type = "cpu"; 50 clocks = <&fll16m>; 51 clock-frequency = <DT_FREQ_M(16)>; 52 riscv,isa = "rv32emc"; 53 nordic,bus-width = <32>; 54 55 cpuppr_vevif_rx: mailbox { 56 compatible = "nordic,nrf-vevif-task-rx"; 57 status = "disabled"; 58 interrupt-parent = <&cpuppr_clic>; 59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, 60 <1 NRF_DEFAULT_IRQ_PRIORITY>, 61 <2 NRF_DEFAULT_IRQ_PRIORITY>, 62 <3 NRF_DEFAULT_IRQ_PRIORITY>, 63 <4 NRF_DEFAULT_IRQ_PRIORITY>, 64 <5 NRF_DEFAULT_IRQ_PRIORITY>, 65 <6 NRF_DEFAULT_IRQ_PRIORITY>, 66 <7 NRF_DEFAULT_IRQ_PRIORITY>, 67 <8 NRF_DEFAULT_IRQ_PRIORITY>, 68 <9 NRF_DEFAULT_IRQ_PRIORITY>, 69 <10 NRF_DEFAULT_IRQ_PRIORITY>, 70 <11 NRF_DEFAULT_IRQ_PRIORITY>, 71 <12 NRF_DEFAULT_IRQ_PRIORITY>, 72 <13 NRF_DEFAULT_IRQ_PRIORITY>, 73 <14 NRF_DEFAULT_IRQ_PRIORITY>, 74 <15 NRF_DEFAULT_IRQ_PRIORITY>; 75 #mbox-cells = <1>; 76 nordic,tasks = <16>; 77 nordic,tasks-mask = <0xfffffff0>; 78 }; 79 }; 80 81 cpuflpr: cpu@e { 82 compatible = "nordic,vpr"; 83 reg = <14>; 84 device_type = "cpu"; 85 clock-frequency = <DT_FREQ_M(320)>; 86 riscv,isa = "rv32emc"; 87 nordic,bus-width = <64>; 88 89 cpuflpr_vevif_rx: mailbox { 90 compatible = "nordic,nrf-vevif-task-rx"; 91 status = "disabled"; 92 interrupt-parent = <&cpuflpr_clic>; 93 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, 94 <1 NRF_DEFAULT_IRQ_PRIORITY>, 95 <2 NRF_DEFAULT_IRQ_PRIORITY>, 96 <3 NRF_DEFAULT_IRQ_PRIORITY>, 97 <4 NRF_DEFAULT_IRQ_PRIORITY>, 98 <5 NRF_DEFAULT_IRQ_PRIORITY>, 99 <6 NRF_DEFAULT_IRQ_PRIORITY>, 100 <7 NRF_DEFAULT_IRQ_PRIORITY>, 101 <8 NRF_DEFAULT_IRQ_PRIORITY>, 102 <9 NRF_DEFAULT_IRQ_PRIORITY>, 103 <10 NRF_DEFAULT_IRQ_PRIORITY>, 104 <11 NRF_DEFAULT_IRQ_PRIORITY>, 105 <12 NRF_DEFAULT_IRQ_PRIORITY>, 106 <13 NRF_DEFAULT_IRQ_PRIORITY>, 107 <14 NRF_DEFAULT_IRQ_PRIORITY>, 108 <15 NRF_DEFAULT_IRQ_PRIORITY>, 109 <16 NRF_DEFAULT_IRQ_PRIORITY>, 110 <17 NRF_DEFAULT_IRQ_PRIORITY>, 111 <18 NRF_DEFAULT_IRQ_PRIORITY>, 112 <19 NRF_DEFAULT_IRQ_PRIORITY>, 113 <20 NRF_DEFAULT_IRQ_PRIORITY>, 114 <21 NRF_DEFAULT_IRQ_PRIORITY>, 115 <22 NRF_DEFAULT_IRQ_PRIORITY>, 116 <23 NRF_DEFAULT_IRQ_PRIORITY>, 117 <24 NRF_DEFAULT_IRQ_PRIORITY>, 118 <25 NRF_DEFAULT_IRQ_PRIORITY>, 119 <26 NRF_DEFAULT_IRQ_PRIORITY>, 120 <27 NRF_DEFAULT_IRQ_PRIORITY>, 121 <28 NRF_DEFAULT_IRQ_PRIORITY>, 122 <29 NRF_DEFAULT_IRQ_PRIORITY>, 123 <30 NRF_DEFAULT_IRQ_PRIORITY>, 124 <31 NRF_DEFAULT_IRQ_PRIORITY>; 125 #mbox-cells = <1>; 126 nordic,tasks = <32>; 127 nordic,tasks-mask = <0xffff0000>; 128 }; 129 }; 130 131 power-states { 132 // substate-id = <0>; is reserved for "idle", cache powered on 133 // substate-id = <1>; is reserved for "idle-cache-retained" 134 idle_cache_disabled: idle_cache_disabled { 135 compatible = "zephyr,power-state"; 136 power-state-name = "suspend-to-idle"; 137 substate-id = <2>; 138 min-residency-us = <1000>; 139 exit-latency-us = <30>; 140 }; 141 s2ram: s2ram { 142 compatible = "zephyr,power-state"; 143 power-state-name = "suspend-to-ram"; 144 min-residency-us = <2000>; 145 exit-latency-us = <260>; 146 }; 147 }; 148 }; 149 150 reserved-memory { 151 #address-cells = <1>; 152 #size-cells = <1>; 153 154 suit_storage_partition: memory@e1ed000 { 155 reg = <0xe1ed000 DT_SIZE_K(20)>; 156 }; 157 }; 158 159 clocks { 160 hfxo: hfxo { 161 compatible = "nordic,nrf54h-hfxo"; 162 status = "disabled"; 163 #clock-cells = <0>; 164 clock-frequency = <DT_FREQ_M(32)>; 165 }; 166 167 lfxo: lfxo { 168 compatible = "nordic,nrf54h-lfxo"; 169 status = "disabled"; 170 #clock-cells = <0>; 171 clock-frequency = <32768>; 172 }; 173 174 fll16m: fll16m { 175 compatible = "nordic,nrf-fll16m"; 176 #clock-cells = <0>; 177 clock-frequency = <DT_FREQ_M(16)>; 178 open-loop-accuracy-ppm = <20000>; 179 closed-loop-base-accuracy-ppm = <5000>; 180 clocks = <&hfxo>, <&lfxo>; 181 clock-names = "hfxo", "lfxo"; 182 }; 183 184 hsfll120: hsfll120 { 185 compatible = "nordic,nrf-hsfll-global"; 186 clocks = <&fll16m>; 187 #clock-cells = <0>; 188 clock-frequency = <320000000>; 189 supported-clock-frequencies = <64000000 190 128000000 191 256000000 192 320000000>; 193 }; 194 195 lfclk: lfclk { 196 compatible = "nordic,nrf-lfclk"; 197 #clock-cells = <0>; 198 clock-frequency = <32768>; 199 status = "okay"; 200 lfrc-accuracy-ppm = <500>; 201 lflprc-accuracy-ppm = <1000>; 202 clocks = <&hfxo>, <&lfxo>; 203 clock-names = "hfxo", "lfxo"; 204 }; 205 }; 206 207 gpd: global-power-domain { 208 compatible = "nordic,nrf-gpd"; 209 #power-domain-cells = <1>; 210 }; 211 212 soc { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 216 mram1x: mram@e000000 { 217 compatible = "nordic,mram"; 218 reg = <0xe000000 DT_SIZE_K(2048)>; 219 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 220 erase-block-size = <4096>; 221 write-block-size = <16>; 222 }; 223 224 cpuapp_uicr: uicr@fff8000 { 225 compatible = "nordic,nrf-uicr-v2"; 226 reg = <0xfff8000 DT_SIZE_K(2)>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0x0 0xfff8000 DT_SIZE_K(2)>; 230 domain = <2>; 231 232 bicr: bicr@7b0 { 233 compatible = "nordic,nrf-bicr"; 234 reg = <0x7b0 48>; 235 }; 236 }; 237 238 cpurad_uicr: uicr@fffa000 { 239 compatible = "nordic,nrf-uicr-v2"; 240 reg = <0xfffa000 DT_SIZE_K(2)>; 241 domain = <3>; 242 }; 243 244 ficr: ficr@fffe000 { 245 compatible = "nordic,nrf-ficr"; 246 reg = <0xfffe000 DT_SIZE_K(2)>; 247 #nordic,ficr-cells = <1>; 248 }; 249 250 cpuapp_ram0: sram@22000000 { 251 compatible = "mmio-sram"; 252 reg = <0x22000000 DT_SIZE_K(32)>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x22000000 0x8000>; 256 }; 257 258 cpurad_ram0: sram@23000000 { 259 compatible = "mmio-sram"; 260 reg = <0x23000000 DT_SIZE_K(192)>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x23000000 0x30000>; 264 }; 265 266 cpuapp_peripherals: peripheral@52000000 { 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges = <0x0 0x52000000 0x1000000>; 270 271 cpuapp_hsfll: clock@d000 { 272 compatible = "nordic,nrf-hsfll-local"; 273 #clock-cells = <0>; 274 reg = <0xd000 0x1000>; 275 clocks = <&fll16m>; 276 clock-frequency = <DT_FREQ_M(320)>; 277 nordic,ficrs = 278 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, 279 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, 280 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; 281 nordic,ficr-names = "vsup", "coarse", "fine"; 282 }; 283 284 cpuapp_ipct: ipct@13000 { 285 compatible = "nordic,nrf-ipct-local"; 286 reg = <0x13000 0x1000>; 287 status = "disabled"; 288 channels = <4>; 289 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 290 <65 NRF_DEFAULT_IRQ_PRIORITY>; 291 }; 292 293 cpuapp_wdt010: watchdog@14000 { 294 compatible = "nordic,nrf-wdt"; 295 reg = <0x14000 0x1000>; 296 status = "disabled"; 297 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 298 clocks = <&lfclk>; 299 }; 300 301 cpuapp_wdt011: watchdog@15000 { 302 compatible = "nordic,nrf-wdt"; 303 reg = <0x15000 0x1000>; 304 status = "disabled"; 305 interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; 306 clocks = <&lfclk>; 307 }; 308 309 cpuapp_resetinfo: resetinfo@1e000 { 310 compatible = "nordic,nrf-resetinfo"; 311 reg = <0x1e000 0x1000>; 312 }; 313 314 cpuapp_ieee802154: ieee802154 { 315 compatible = "nordic,nrf-ieee802154"; 316 status = "disabled"; 317 }; 318 }; 319 320 cpurad_peripherals: peripheral@53000000 { 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x53000000 0x1000000>; 324 325 cpurad_hsfll: clock@d000 { 326 compatible = "nordic,nrf-hsfll-local"; 327 #clock-cells = <0>; 328 reg = <0xd000 0x1000>; 329 clocks = <&fll16m>; 330 clock-frequency = <DT_FREQ_M(256)>; 331 nordic,ficrs = 332 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, 333 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, 334 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; 335 nordic,ficr-names = "vsup", "coarse", "fine"; 336 }; 337 338 cpurad_wdt010: watchdog@13000 { 339 compatible = "nordic,nrf-wdt"; 340 reg = <0x13000 0x1000>; 341 status = "disabled"; 342 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 343 clocks = <&lfclk>; 344 }; 345 346 cpurad_wdt011: watchdog@14000 { 347 compatible = "nordic,nrf-wdt"; 348 reg = <0x14000 0x1000>; 349 status = "disabled"; 350 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 351 clocks = <&lfclk>; 352 }; 353 354 cpurad_resetinfo: resetinfo@1e000 { 355 compatible = "nordic,nrf-resetinfo"; 356 reg = <0x1e000 0x1000>; 357 }; 358 359 dppic020: dppic@22000 { 360 compatible = "nordic,nrf-dppic-local"; 361 reg = <0x22000 0x1000>; 362 status = "disabled"; 363 }; 364 365 cpurad_ipct: ipct@24000 { 366 compatible = "nordic,nrf-ipct-local"; 367 reg = <0x24000 0x1000>; 368 status = "disabled"; 369 channels = <8>; 370 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 371 <65 NRF_DEFAULT_IRQ_PRIORITY>; 372 }; 373 374 egu020: egu@25000 { 375 compatible = "nordic,nrf-egu"; 376 reg = <0x25000 0x1000>; 377 status = "disabled"; 378 interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; 379 }; 380 381 timer020: timer@28000 { 382 compatible = "nordic,nrf-timer"; 383 reg = <0x28000 0x1000>; 384 status = "disabled"; 385 cc-num = <8>; 386 interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; 387 clocks = <&fll16m>; 388 max-bit-width = <32>; 389 max-frequency = <DT_FREQ_M(32)>; 390 prescaler = <0>; 391 }; 392 393 timer021: timer@29000 { 394 compatible = "nordic,nrf-timer"; 395 reg = <0x29000 0x1000>; 396 status = "disabled"; 397 cc-num = <8>; 398 interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; 399 clocks = <&fll16m>; 400 max-bit-width = <32>; 401 max-frequency = <DT_FREQ_M(32)>; 402 prescaler = <0>; 403 }; 404 405 timer022: timer@2a000 { 406 compatible = "nordic,nrf-timer"; 407 reg = <0x2a000 0x1000>; 408 status = "disabled"; 409 cc-num = <8>; 410 interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; 411 clocks = <&fll16m>; 412 max-bit-width = <32>; 413 max-frequency = <DT_FREQ_M(32)>; 414 prescaler = <0>; 415 }; 416 417 rtc: rtc@2b000 { 418 compatible = "nordic,nrf-rtc"; 419 reg = <0x2b000 0x1000>; 420 status = "disabled"; 421 cc-num = <4>; 422 clock-frequency = <32768>; 423 interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; 424 clocks = <&lfclk>; 425 prescaler = <1>; 426 }; 427 428 radio: radio@2c000 { 429 compatible = "nordic,nrf-radio"; 430 reg = <0x2c000 0x1000>; 431 status = "disabled"; 432 ble-2mbps-supported; 433 ble-coded-phy-supported; 434 cs-supported; 435 dfe-supported; 436 ieee802154-supported; 437 interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; 438 clocks = <&hfxo>; 439 440 cpurad_ieee802154: ieee802154 { 441 compatible = "nordic,nrf-ieee802154"; 442 status = "disabled"; 443 }; 444 }; 445 446 ccm030: ccm@3a000 { 447 compatible = "nordic,nrf-ccm"; 448 reg = <0x3a000 0x1000>; 449 interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; 450 status = "disabled"; 451 }; 452 453 ecb030: ecb@3b000 { 454 compatible = "nordic,nrf-ecb"; 455 reg = <0x3b000 0x1000>; 456 interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; 457 status = "disabled"; 458 }; 459 460 ccm031: ccm@3c000 { 461 compatible = "nordic,nrf-ccm"; 462 reg = <0x3c000 0x1000>; 463 interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; 464 status = "disabled"; 465 }; 466 467 ecb031: ecb@3d000 { 468 compatible = "nordic,nrf-ecb"; 469 reg = <0x3d000 0x1000>; 470 status = "disabled"; 471 interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; 472 }; 473 }; 474 475 tdd_peripherals: peripheral@bf000000 { 476 #address-cells = <1>; 477 #size-cells = <1>; 478 ranges = <0x0 0xbf000000 0x1000000>; 479 480 tbm: tbm@3000 { 481 compatible = "nordic,nrf-tbm"; 482 reg = <0x3000 0x408>; 483 status = "disabled"; 484 interrupts = <127 NRF_DEFAULT_IRQ_PRIORITY>; 485 }; 486 487 tddconf: tddconf@1000 { 488 compatible = "nordic,nrf-tddconf"; 489 reg = <0x1000 0x10>; 490 status = "disabled"; 491 }; 492 }; 493 494 global_peripherals: peripheral@5f000000 { 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0x0 0x5f000000 0x1000000>; 498 499 usbhs: usbhs@86000 { 500 compatible = "nordic,nrf-usbhs", "snps,dwc2"; 501 reg = <0x86000 0x1000>, <0x2f700000 0x40000>; 502 reg-names = "wrapper", "core"; 503 interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; 504 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 505 num-in-eps = <8>; 506 num-out-eps = <10>; 507 ghwcfg1 = <0xaa555000>; 508 ghwcfg2 = <0x22abfc72>; 509 ghwcfg4 = <0x1e10aa60>; 510 status = "disabled"; 511 }; 512 513 exmif: spi@95000 { 514 compatible = "nordic,nrf-exmif"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0x95000 0x500 0x95500 0xb00>; 518 reg-names = "wrapper", "core"; 519 interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; 520 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 521 clock-frequency = <DT_FREQ_M(400)>; 522 fifo-depth = <32>; 523 max-xfer-size = <16>; 524 status = "disabled"; 525 }; 526 527 cpusec_bellboard: mailbox@99000 { 528 reg = <0x99000 0x1000>; 529 status = "disabled"; 530 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 531 #mbox-cells = <1>; 532 }; 533 534 cpuapp_bellboard: mailbox@9a000 { 535 reg = <0x9a000 0x1000>; 536 status = "disabled"; 537 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 538 #mbox-cells = <1>; 539 }; 540 541 cpurad_bellboard: mailbox@9b000 { 542 reg = <0x9b000 0x1000>; 543 status = "disabled"; 544 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 545 #mbox-cells = <1>; 546 }; 547 548 canpll: clock-controller@8c2000{ 549 compatible = "nordic,nrf-auxpll"; 550 reg = <0x8c2000 0x1000>; 551 interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; 552 clocks = <&hfxo>; 553 #clock-cells = <0>; 554 nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>; 555 nordic,frequency = <0>; 556 nordic,out-div = <2>; 557 nordic,out-drive = <0>; 558 nordic,current-tune = <6>; 559 nordic,sdm-disable; 560 nordic,range = "high"; 561 status = "disabled"; 562 }; 563 564 cpusys_vevif_tx: mailbox@8c8000 { 565 compatible = "nordic,nrf-vevif-task-tx"; 566 reg = <0x8c8000 0x1000>; 567 status = "disabled"; 568 #mbox-cells = <1>; 569 nordic,tasks = <32>; 570 nordic,tasks-mask = <0xfffff0ff>; 571 }; 572 573 ipct120: ipct@8d1000 { 574 compatible = "nordic,nrf-ipct-global"; 575 reg = <0x8d1000 0x1000>; 576 status = "disabled"; 577 channels = <8>; 578 global-domain-id = <12>; 579 }; 580 581 cpuflpr_vpr: vpr@8d4000 { 582 compatible = "nordic,nrf-vpr-coprocessor"; 583 reg = <0x8d4000 0x1000>; 584 status = "disabled"; 585 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0x0 0x8d4000 0x1000>; 589 590 cpuflpr_vevif_tx: mailbox@0 { 591 compatible = "nordic,nrf-vevif-task-tx"; 592 reg = <0x0 0x1000>; 593 status = "disabled"; 594 #mbox-cells = <1>; 595 nordic,tasks = <32>; 596 nordic,tasks-mask = <0xffff0000>; 597 }; 598 }; 599 600 can120: can@8d8000 { 601 compatible = "nordic,nrf-can"; 602 reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>; 603 reg-names = "wrapper", "m_can", "message_ram"; 604 interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>; 605 clocks = <&canpll>; 606 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 607 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; 608 status = "disabled"; 609 }; 610 611 dppic120: dppic@8e1000 { 612 compatible = "nordic,nrf-dppic-global"; 613 reg = <0x8e1000 0x1000>; 614 status = "disabled"; 615 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 616 }; 617 618 timer120: timer@8e2000 { 619 compatible = "nordic,nrf-timer"; 620 reg = <0x8e2000 0x1000>; 621 status = "disabled"; 622 cc-num = <6>; 623 interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; 624 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 625 max-bit-width = <32>; 626 max-frequency = <DT_FREQ_M(320)>; 627 prescaler = <0>; 628 }; 629 630 timer121: timer@8e3000 { 631 compatible = "nordic,nrf-timer"; 632 reg = <0x8e3000 0x1000>; 633 status = "disabled"; 634 cc-num = <6>; 635 interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; 636 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 637 max-bit-width = <32>; 638 max-frequency = <DT_FREQ_M(320)>; 639 prescaler = <0>; 640 }; 641 642 pwm120: pwm@8e4000 { 643 compatible = "nordic,nrf-pwm"; 644 reg = <0x8e4000 0x1000>; 645 status = "disabled"; 646 interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; 647 clocks = <&hsfll120>; 648 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 649 #pwm-cells = <3>; 650 }; 651 652 spi120: spi@8e6000 { 653 compatible = "nordic,nrf-spim"; 654 reg = <0x8e6000 0x1000>; 655 status = "disabled"; 656 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 657 easydma-maxcnt-bits = <15>; 658 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 659 clocks = <&hsfll120>; 660 max-frequency = <DT_FREQ_M(32)>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 rx-delay-supported; 664 rx-delay = <1>; 665 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 666 <NRF_FUN_SPIS_SCK>; 667 }; 668 669 uart120: uart@8e6000 { 670 compatible = "nordic,nrf-uarte"; 671 reg = <0x8e6000 0x1000>; 672 status = "disabled"; 673 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 674 clocks = <&hsfll120>; 675 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 676 endtx-stoptx-supported; 677 frame-timeout-supported; 678 }; 679 680 spi121: spi@8e7000 { 681 compatible = "nordic,nrf-spim"; 682 reg = <0x8e7000 0x1000>; 683 status = "disabled"; 684 easydma-maxcnt-bits = <15>; 685 interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; 686 clocks = <&hsfll120>; 687 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 688 max-frequency = <DT_FREQ_M(32)>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 rx-delay-supported; 692 rx-delay = <1>; 693 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 694 <NRF_FUN_SPIS_SCK>; 695 }; 696 697 cpuppr_vpr: vpr@908000 { 698 compatible = "nordic,nrf-vpr-coprocessor"; 699 reg = <0x908000 0x1000>; 700 status = "disabled"; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges = <0x0 0x908000 0x1000>; 704 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 705 706 cpuppr_vevif_tx: mailbox@0 { 707 compatible = "nordic,nrf-vevif-task-tx"; 708 reg = <0x0 0x1000>; 709 status = "disabled"; 710 #mbox-cells = <1>; 711 nordic,tasks = <16>; 712 nordic,tasks-mask = <0xfffffff0>; 713 }; 714 }; 715 716 ipct130: ipct@921000 { 717 compatible = "nordic,nrf-ipct-global"; 718 reg = <0x921000 0x1000>; 719 status = "disabled"; 720 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 721 channels = <8>; 722 global-domain-id = <13>; 723 }; 724 725 dppic130: dppic@922000 { 726 compatible = "nordic,nrf-dppic-global"; 727 reg = <0x922000 0x1000>; 728 status = "disabled"; 729 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 730 }; 731 732 rtc130: rtc@928000 { 733 compatible = "nordic,nrf-rtc"; 734 reg = <0x928000 0x1000>; 735 status = "disabled"; 736 cc-num = <4>; 737 clock-frequency = <32768>; 738 interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; 739 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 740 clocks = <&lfclk>; 741 prescaler = <1>; 742 }; 743 744 rtc131: rtc@929000 { 745 compatible = "nordic,nrf-rtc"; 746 reg = <0x929000 0x1000>; 747 status = "disabled"; 748 cc-num = <4>; 749 clock-frequency = <32768>; 750 interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; 751 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 752 clocks = <&lfclk>; 753 prescaler = <1>; 754 }; 755 756 wdt131: watchdog@92b000 { 757 compatible = "nordic,nrf-wdt"; 758 reg = <0x92b000 0x1000>; 759 status = "disabled"; 760 interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; 761 clocks = <&lfclk>; 762 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 763 }; 764 765 wdt132: watchdog@92c000 { 766 compatible = "nordic,nrf-wdt"; 767 reg = <0x92c000 0x1000>; 768 status = "disabled"; 769 interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; 770 clocks = <&lfclk>; 771 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 772 }; 773 774 egu130: egu@92d000 { 775 compatible = "nordic,nrf-egu"; 776 reg = <0x92d000 0x1000>; 777 status = "disabled"; 778 interrupts = <301 NRF_DEFAULT_IRQ_PRIORITY>; 779 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 780 }; 781 782 gpiote130: gpiote@934000 { 783 compatible = "nordic,nrf-gpiote"; 784 reg = <0x934000 0x1000>; 785 status = "disabled"; 786 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 787 instance = <130>; 788 }; 789 790 gpio0: gpio@938000 { 791 compatible = "nordic,nrf-gpio"; 792 reg = <0x938000 0x200>; 793 status = "disabled"; 794 #gpio-cells = <2>; 795 gpio-controller; 796 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 797 gpiote-instance = <&gpiote130>; 798 ngpios = <12>; 799 port = <0>; 800 }; 801 802 gpio1: gpio@938200 { 803 compatible = "nordic,nrf-gpio"; 804 reg = <0x938200 0x200>; 805 status = "disabled"; 806 #gpio-cells = <2>; 807 gpio-controller; 808 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 809 gpiote-instance = <&gpiote130>; 810 ngpios = <12>; 811 port = <1>; 812 }; 813 814 gpio2: gpio@938400 { 815 compatible = "nordic,nrf-gpio"; 816 reg = <0x938400 0x200>; 817 status = "disabled"; 818 #gpio-cells = <2>; 819 gpio-controller; 820 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 821 gpiote-instance = <&gpiote130>; 822 ngpios = <12>; 823 port = <2>; 824 }; 825 826 gpio6: gpio@938c00 { 827 compatible = "nordic,nrf-gpio"; 828 reg = <0x938c00 0x200>; 829 status = "disabled"; 830 #gpio-cells = <2>; 831 gpio-controller; 832 power-domains = <&gpd NRF_GPD_SLOW_MAIN>, 833 <&gpd NRF_GPD_FAST_ACTIVE1>; 834 power-domain-names = "peripheral", "pad"; 835 ngpios = <14>; 836 port = <6>; 837 }; 838 839 gpio7: gpio@938e00 { 840 compatible = "nordic,nrf-gpio"; 841 reg = <0x938e00 0x200>; 842 status = "disabled"; 843 #gpio-cells = <2>; 844 gpio-controller; 845 power-domains = <&gpd NRF_GPD_SLOW_MAIN>, 846 <&gpd NRF_GPD_FAST_ACTIVE1>; 847 power-domain-names = "peripheral", "pad"; 848 ngpios = <8>; 849 port = <7>; 850 }; 851 852 gpio9: gpio@939200 { 853 compatible = "nordic,nrf-gpio"; 854 reg = <0x939200 0x200>; 855 status = "disabled"; 856 #gpio-cells = <2>; 857 gpio-controller; 858 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 859 gpiote-instance = <&gpiote130>; 860 ngpios = <6>; 861 port = <9>; 862 }; 863 864 dppic131: dppic@981000 { 865 compatible = "nordic,nrf-dppic-global"; 866 reg = <0x981000 0x1000>; 867 status = "disabled"; 868 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 869 }; 870 871 adc: adc@982000 { 872 compatible = "nordic,nrf-saadc"; 873 reg = <0x982000 0x1000>; 874 interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; 875 status = "disabled"; 876 #io-channel-cells = <1>; 877 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 878 }; 879 880 comp: comparator@983000 { 881 /* 882 * Use compatible "nordic,nrf-comp" to configure as COMP 883 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP 884 */ 885 compatible = "nordic,nrf-comp"; 886 reg = <0x983000 0x1000>; 887 status = "disabled"; 888 interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; 889 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 890 }; 891 892 temp: temperature-sensor@984000 { 893 compatible = "nordic,nrf-temp"; 894 reg = <0x984000 0x1000>; 895 interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; 896 status = "disabled"; 897 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 898 }; 899 900 nfct: nfct@985000 { 901 compatible = "nordic,nrf-nfct"; 902 reg = <0x985000 0x1000>; 903 status = "disabled"; 904 interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; 905 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 906 }; 907 908 dppic132: dppic@991000 { 909 compatible = "nordic,nrf-dppic-global"; 910 reg = <0x991000 0x1000>; 911 status = "disabled"; 912 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 913 }; 914 915 pdm0: pdm@993000 { 916 compatible = "nordic,nrf-pdm"; 917 reg = <0x993000 0x1000>; 918 status = "disabled"; 919 interrupts = <403 NRF_DEFAULT_IRQ_PRIORITY>; 920 nordic,clockpin-enable = <NRF_FUN_PDM_CLK>; 921 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 922 }; 923 924 qdec130: qdec@994000 { 925 compatible = "nordic,nrf-qdec"; 926 reg = <0x994000 0x1000>; 927 status = "disabled"; 928 interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; 929 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 930 }; 931 932 qdec131: qdec@995000 { 933 compatible = "nordic,nrf-qdec"; 934 reg = <0x995000 0x1000>; 935 status = "disabled"; 936 interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; 937 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 938 }; 939 940 grtc: grtc@99c000 { 941 compatible = "nordic,nrf-grtc"; 942 reg = <0x99c000 0x1000>; 943 status = "disabled"; 944 cc-num = <16>; 945 /* GRTC uses both LFCLK and FLL16M, but its accuracy and 946 * precision are inherited from LFCLK. that's why this 947 * one is linked here. 948 */ 949 clocks = <&lfclk>; 950 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 951 }; 952 953 dppic133: dppic@9a1000 { 954 compatible = "nordic,nrf-dppic-global"; 955 reg = <0x9a1000 0x1000>; 956 status = "disabled"; 957 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 958 }; 959 960 timer130: timer@9a2000 { 961 compatible = "nordic,nrf-timer"; 962 reg = <0x9a2000 0x1000>; 963 status = "disabled"; 964 cc-num = <6>; 965 interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; 966 clocks = <&fll16m>; 967 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 968 max-bit-width = <32>; 969 prescaler = <0>; 970 }; 971 972 timer131: timer@9a3000 { 973 compatible = "nordic,nrf-timer"; 974 reg = <0x9a3000 0x1000>; 975 status = "disabled"; 976 cc-num = <6>; 977 interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; 978 clocks = <&fll16m>; 979 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 980 max-bit-width = <32>; 981 prescaler = <0>; 982 }; 983 984 pwm130: pwm@9a4000 { 985 compatible = "nordic,nrf-pwm"; 986 reg = <0x9a4000 0x1000>; 987 status = "disabled"; 988 interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; 989 clocks = <&fll16m>; 990 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 991 #pwm-cells = <3>; 992 }; 993 994 i2c130: i2c@9a5000 { 995 compatible = "nordic,nrf-twim"; 996 reg = <0x9a5000 0x1000>; 997 status = "disabled"; 998 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 999 clocks = <&fll16m>; 1000 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1001 easydma-maxcnt-bits = <15>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1005 <NRF_FUN_TWIM_SCL>; 1006 zephyr,pm-device-runtime-auto; 1007 }; 1008 1009 spi130: spi@9a5000 { 1010 compatible = "nordic,nrf-spim"; 1011 reg = <0x9a5000 0x1000>; 1012 status = "disabled"; 1013 easydma-maxcnt-bits = <15>; 1014 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 1015 clocks = <&fll16m>; 1016 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1017 max-frequency = <DT_FREQ_M(8)>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 rx-delay-supported; 1021 rx-delay = <1>; 1022 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1023 <NRF_FUN_SPIM_SCK>, 1024 <NRF_FUN_SPIS_MISO>, 1025 <NRF_FUN_SPIS_SCK>; 1026 }; 1027 1028 uart130: uart@9a5000 { 1029 compatible = "nordic,nrf-uarte"; 1030 reg = <0x9a5000 0x1000>; 1031 status = "disabled"; 1032 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 1033 clocks = <&fll16m>; 1034 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1035 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1036 endtx-stoptx-supported; 1037 frame-timeout-supported; 1038 }; 1039 1040 i2c131: i2c@9a6000 { 1041 compatible = "nordic,nrf-twim"; 1042 reg = <0x9a6000 0x1000>; 1043 status = "disabled"; 1044 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1045 clocks = <&fll16m>; 1046 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1047 easydma-maxcnt-bits = <15>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1051 <NRF_FUN_TWIM_SCL>; 1052 zephyr,pm-device-runtime-auto; 1053 }; 1054 1055 spi131: spi@9a6000 { 1056 compatible = "nordic,nrf-spim"; 1057 reg = <0x9a6000 0x1000>; 1058 status = "disabled"; 1059 easydma-maxcnt-bits = <15>; 1060 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1061 clocks = <&fll16m>; 1062 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1063 max-frequency = <DT_FREQ_M(8)>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 rx-delay-supported; 1067 rx-delay = <1>; 1068 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1069 <NRF_FUN_SPIM_SCK>, 1070 <NRF_FUN_SPIS_MISO>, 1071 <NRF_FUN_SPIS_SCK>; 1072 }; 1073 1074 uart131: uart@9a6000 { 1075 compatible = "nordic,nrf-uarte"; 1076 reg = <0x9a6000 0x1000>; 1077 status = "disabled"; 1078 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1079 clocks = <&fll16m>; 1080 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1081 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1082 endtx-stoptx-supported; 1083 frame-timeout-supported; 1084 }; 1085 1086 dppic134: dppic@9b1000 { 1087 compatible = "nordic,nrf-dppic-global"; 1088 reg = <0x9b1000 0x1000>; 1089 status = "disabled"; 1090 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1091 }; 1092 1093 timer132: timer@9b2000 { 1094 compatible = "nordic,nrf-timer"; 1095 reg = <0x9b2000 0x1000>; 1096 status = "disabled"; 1097 cc-num = <6>; 1098 interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; 1099 clocks = <&fll16m>; 1100 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1101 max-bit-width = <32>; 1102 prescaler = <0>; 1103 }; 1104 1105 timer133: timer@9b3000 { 1106 compatible = "nordic,nrf-timer"; 1107 reg = <0x9b3000 0x1000>; 1108 status = "disabled"; 1109 cc-num = <6>; 1110 interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; 1111 clocks = <&fll16m>; 1112 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1113 max-bit-width = <32>; 1114 prescaler = <0>; 1115 }; 1116 1117 pwm131: pwm@9b4000 { 1118 compatible = "nordic,nrf-pwm"; 1119 reg = <0x9b4000 0x1000>; 1120 status = "disabled"; 1121 interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; 1122 clocks = <&fll16m>; 1123 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1124 #pwm-cells = <3>; 1125 }; 1126 1127 i2c132: i2c@9b5000 { 1128 compatible = "nordic,nrf-twim"; 1129 reg = <0x9b5000 0x1000>; 1130 status = "disabled"; 1131 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1132 clocks = <&fll16m>; 1133 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1134 easydma-maxcnt-bits = <15>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1138 <NRF_FUN_TWIM_SCL>; 1139 zephyr,pm-device-runtime-auto; 1140 }; 1141 1142 spi132: spi@9b5000 { 1143 compatible = "nordic,nrf-spim"; 1144 reg = <0x9b5000 0x1000>; 1145 status = "disabled"; 1146 easydma-maxcnt-bits = <15>; 1147 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1148 clocks = <&fll16m>; 1149 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1150 max-frequency = <DT_FREQ_M(8)>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 rx-delay-supported; 1154 rx-delay = <1>; 1155 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1156 <NRF_FUN_SPIM_SCK>, 1157 <NRF_FUN_SPIS_MISO>, 1158 <NRF_FUN_SPIS_SCK>; 1159 }; 1160 1161 uart132: uart@9b5000 { 1162 compatible = "nordic,nrf-uarte"; 1163 reg = <0x9b5000 0x1000>; 1164 status = "disabled"; 1165 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1166 clocks = <&fll16m>; 1167 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1168 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1169 endtx-stoptx-supported; 1170 frame-timeout-supported; 1171 }; 1172 1173 i2c133: i2c@9b6000 { 1174 compatible = "nordic,nrf-twim"; 1175 reg = <0x9b6000 0x1000>; 1176 status = "disabled"; 1177 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1178 clocks = <&fll16m>; 1179 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1180 easydma-maxcnt-bits = <15>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1184 <NRF_FUN_TWIM_SCL>; 1185 zephyr,pm-device-runtime-auto; 1186 }; 1187 1188 spi133: spi@9b6000 { 1189 compatible = "nordic,nrf-spim"; 1190 reg = <0x9b6000 0x1000>; 1191 status = "disabled"; 1192 easydma-maxcnt-bits = <15>; 1193 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1194 clocks = <&fll16m>; 1195 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1196 max-frequency = <DT_FREQ_M(8)>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 rx-delay-supported; 1200 rx-delay = <1>; 1201 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1202 <NRF_FUN_SPIM_SCK>, 1203 <NRF_FUN_SPIS_MISO>, 1204 <NRF_FUN_SPIS_SCK>; 1205 }; 1206 1207 uart133: uart@9b6000 { 1208 compatible = "nordic,nrf-uarte"; 1209 reg = <0x9b6000 0x1000>; 1210 status = "disabled"; 1211 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1212 clocks = <&fll16m>; 1213 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1214 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1215 endtx-stoptx-supported; 1216 frame-timeout-supported; 1217 }; 1218 1219 dppic135: dppic@9c1000 { 1220 compatible = "nordic,nrf-dppic-global"; 1221 reg = <0x9c1000 0x1000>; 1222 status = "disabled"; 1223 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1224 }; 1225 1226 timer134: timer@9c2000 { 1227 compatible = "nordic,nrf-timer"; 1228 reg = <0x9c2000 0x1000>; 1229 status = "disabled"; 1230 cc-num = <6>; 1231 interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; 1232 clocks = <&fll16m>; 1233 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1234 max-bit-width = <32>; 1235 prescaler = <0>; 1236 }; 1237 1238 timer135: timer@9c3000 { 1239 compatible = "nordic,nrf-timer"; 1240 reg = <0x9c3000 0x1000>; 1241 status = "disabled"; 1242 cc-num = <6>; 1243 interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; 1244 clocks = <&fll16m>; 1245 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1246 max-bit-width = <32>; 1247 prescaler = <0>; 1248 }; 1249 1250 pwm132: pwm@9c4000 { 1251 compatible = "nordic,nrf-pwm"; 1252 reg = <0x9c4000 0x1000>; 1253 status = "disabled"; 1254 interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; 1255 clocks = <&fll16m>; 1256 #pwm-cells = <3>; 1257 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1258 }; 1259 1260 i2c134: i2c@9c5000 { 1261 compatible = "nordic,nrf-twim"; 1262 reg = <0x9c5000 0x1000>; 1263 status = "disabled"; 1264 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1265 clocks = <&fll16m>; 1266 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1267 easydma-maxcnt-bits = <15>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1271 <NRF_FUN_TWIM_SCL>; 1272 zephyr,pm-device-runtime-auto; 1273 }; 1274 1275 spi134: spi@9c5000 { 1276 compatible = "nordic,nrf-spim"; 1277 reg = <0x9c5000 0x1000>; 1278 status = "disabled"; 1279 easydma-maxcnt-bits = <15>; 1280 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1281 clocks = <&fll16m>; 1282 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1283 max-frequency = <DT_FREQ_M(8)>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 rx-delay-supported; 1287 rx-delay = <1>; 1288 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1289 <NRF_FUN_SPIM_SCK>, 1290 <NRF_FUN_SPIS_MISO>, 1291 <NRF_FUN_SPIS_SCK>; 1292 }; 1293 1294 uart134: uart@9c5000 { 1295 compatible = "nordic,nrf-uarte"; 1296 reg = <0x9c5000 0x1000>; 1297 status = "disabled"; 1298 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1299 clocks = <&fll16m>; 1300 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1301 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1302 endtx-stoptx-supported; 1303 frame-timeout-supported; 1304 }; 1305 1306 i2c135: i2c@9c6000 { 1307 compatible = "nordic,nrf-twim"; 1308 reg = <0x9c6000 0x1000>; 1309 status = "disabled"; 1310 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1311 clocks = <&fll16m>; 1312 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1313 easydma-maxcnt-bits = <15>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1317 <NRF_FUN_TWIM_SCL>; 1318 zephyr,pm-device-runtime-auto; 1319 }; 1320 1321 spi135: spi@9c6000 { 1322 compatible = "nordic,nrf-spim"; 1323 reg = <0x9c6000 0x1000>; 1324 status = "disabled"; 1325 easydma-maxcnt-bits = <15>; 1326 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1327 clocks = <&fll16m>; 1328 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1329 max-frequency = <DT_FREQ_M(8)>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 rx-delay-supported; 1333 rx-delay = <1>; 1334 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1335 <NRF_FUN_SPIM_SCK>, 1336 <NRF_FUN_SPIS_MISO>, 1337 <NRF_FUN_SPIS_SCK>; 1338 }; 1339 1340 uart135: uart@9c6000 { 1341 compatible = "nordic,nrf-uarte"; 1342 reg = <0x9c6000 0x1000>; 1343 status = "disabled"; 1344 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1345 clocks = <&fll16m>; 1346 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1347 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1348 endtx-stoptx-supported; 1349 frame-timeout-supported; 1350 }; 1351 1352 dppic136: dppic@9d1000 { 1353 compatible = "nordic,nrf-dppic-global"; 1354 reg = <0x9d1000 0x1000>; 1355 status = "disabled"; 1356 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1357 }; 1358 1359 timer136: timer@9d2000 { 1360 compatible = "nordic,nrf-timer"; 1361 reg = <0x9d2000 0x1000>; 1362 status = "disabled"; 1363 cc-num = <6>; 1364 interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; 1365 clocks = <&fll16m>; 1366 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1367 max-bit-width = <32>; 1368 prescaler = <0>; 1369 }; 1370 1371 timer137: timer@9d3000 { 1372 compatible = "nordic,nrf-timer"; 1373 reg = <0x9d3000 0x1000>; 1374 status = "disabled"; 1375 cc-num = <6>; 1376 interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; 1377 clocks = <&fll16m>; 1378 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1379 max-bit-width = <32>; 1380 prescaler = <0>; 1381 }; 1382 1383 pwm133: pwm@9d4000 { 1384 compatible = "nordic,nrf-pwm"; 1385 reg = <0x9d4000 0x1000>; 1386 status = "disabled"; 1387 interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; 1388 clocks = <&fll16m>; 1389 #pwm-cells = <3>; 1390 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1391 }; 1392 1393 i2c136: i2c@9d5000 { 1394 compatible = "nordic,nrf-twim"; 1395 reg = <0x9d5000 0x1000>; 1396 status = "disabled"; 1397 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1398 clocks = <&fll16m>; 1399 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1400 easydma-maxcnt-bits = <15>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1404 <NRF_FUN_TWIM_SCL>; 1405 zephyr,pm-device-runtime-auto; 1406 }; 1407 1408 spi136: spi@9d5000 { 1409 compatible = "nordic,nrf-spim"; 1410 reg = <0x9d5000 0x1000>; 1411 status = "disabled"; 1412 easydma-maxcnt-bits = <15>; 1413 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1414 clocks = <&fll16m>; 1415 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1416 max-frequency = <DT_FREQ_M(8)>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 rx-delay-supported; 1420 rx-delay = <1>; 1421 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1422 <NRF_FUN_SPIM_SCK>, 1423 <NRF_FUN_SPIS_MISO>, 1424 <NRF_FUN_SPIS_SCK>; 1425 }; 1426 1427 uart136: uart@9d5000 { 1428 compatible = "nordic,nrf-uarte"; 1429 reg = <0x9d5000 0x1000>; 1430 status = "disabled"; 1431 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1432 clocks = <&fll16m>; 1433 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1434 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1435 endtx-stoptx-supported; 1436 frame-timeout-supported; 1437 }; 1438 1439 i2c137: i2c@9d6000 { 1440 compatible = "nordic,nrf-twim"; 1441 reg = <0x9d6000 0x1000>; 1442 status = "disabled"; 1443 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1444 clocks = <&fll16m>; 1445 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1446 easydma-maxcnt-bits = <15>; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1450 <NRF_FUN_TWIM_SCL>; 1451 zephyr,pm-device-runtime-auto; 1452 }; 1453 1454 spi137: spi@9d6000 { 1455 compatible = "nordic,nrf-spim"; 1456 reg = <0x9d6000 0x1000>; 1457 status = "disabled"; 1458 easydma-maxcnt-bits = <15>; 1459 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1460 clocks = <&fll16m>; 1461 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1462 max-frequency = <DT_FREQ_M(8)>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 rx-delay-supported; 1466 rx-delay = <1>; 1467 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1468 <NRF_FUN_SPIM_SCK>, 1469 <NRF_FUN_SPIS_MISO>, 1470 <NRF_FUN_SPIS_SCK>; 1471 }; 1472 1473 uart137: uart@9d6000 { 1474 compatible = "nordic,nrf-uarte"; 1475 reg = <0x9d6000 0x1000>; 1476 status = "disabled"; 1477 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1478 clocks = <&fll16m>; 1479 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1480 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1481 endtx-stoptx-supported; 1482 frame-timeout-supported; 1483 }; 1484 }; 1485 }; 1486 1487 cpuapp_ppb: cpuapp-ppb-bus { 1488 #address-cells = <1>; 1489 #size-cells = <1>; 1490 1491 cpuapp_systick: timer@e000e010 { 1492 compatible = "arm,armv8m-systick"; 1493 reg = <0xe000e010 0x10>; 1494 status = "disabled"; 1495 }; 1496 1497 cpuapp_nvic: interrupt-controller@e000e100 { 1498 compatible = "arm,v8m-nvic"; 1499 reg = <0xe000e100 0xc00>; 1500 arm,num-irq-priority-bits = <3>; 1501 #interrupt-cells = <2>; 1502 interrupt-controller; 1503 #address-cells = <1>; 1504 }; 1505 }; 1506 1507 cpurad_ppb: cpurad-ppb-bus { 1508 #address-cells = <1>; 1509 #size-cells = <1>; 1510 1511 cpurad_systick: timer@e000e010 { 1512 compatible = "arm,armv8m-systick"; 1513 reg = <0xe000e010 0x10>; 1514 status = "disabled"; 1515 }; 1516 1517 cpurad_nvic: interrupt-controller@e000e100 { 1518 compatible = "arm,v8m-nvic"; 1519 reg = <0xe000e100 0xc00>; 1520 arm,num-irq-priority-bits = <3>; 1521 #interrupt-cells = <2>; 1522 interrupt-controller; 1523 #address-cells = <1>; 1524 }; 1525 }; 1526 1527 cpuppr_private: cpuppr-private-bus { 1528 #address-cells = <1>; 1529 #size-cells = <1>; 1530 1531 cpuppr_clic: interrupt-controller@f0000000 { 1532 compatible = "nordic,nrf-clic"; 1533 reg = <0xf0000000 0x3000>; 1534 status = "disabled"; 1535 #interrupt-cells = <2>; 1536 interrupt-controller; 1537 #address-cells = <1>; 1538 }; 1539 }; 1540 1541 cpuflpr_private: cpuflpr-private-bus { 1542 #address-cells = <1>; 1543 #size-cells = <1>; 1544 1545 cpuflpr_clic: interrupt-controller@f0000000 { 1546 compatible = "nordic,nrf-clic"; 1547 reg = <0xf0000000 0x3000>; 1548 status = "disabled"; 1549 #interrupt-cells = <2>; 1550 interrupt-controller; 1551 #address-cells = <1>; 1552 }; 1553 }; 1554 1555 temp_nrfs: temp { 1556 compatible = "nordic,nrf-temp-nrfs"; 1557 status = "disabled"; 1558 }; 1559}; 1560
