1/* 2 * Copyright (c) 2019 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <nordic/nrf_common.dtsi> 9 10/ { 11 chosen { 12 zephyr,bt-hci = &bt_hci_controller; 13 zephyr,entropy = &rng; 14 zephyr,flash-controller = &flash_controller; 15 }; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@1 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-m33"; 24 reg = <1>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 mpu: mpu@e000ed90 { 29 compatible = "arm,armv8m-mpu"; 30 reg = <0xe000ed90 0x40>; 31 }; 32 }; 33 }; 34 35 soc { 36 ficr: ficr@1ff0000 { 37 compatible = "nordic,nrf-ficr"; 38 reg = <0x01ff0000 0x1000>; 39 #nordic,ficr-cells = <1>; 40 status = "okay"; 41 }; 42 43 uicr: uicr@1ff8000 { 44 compatible = "nordic,nrf-uicr"; 45 reg = <0x01ff8000 0x1000>; 46 status = "okay"; 47 }; 48 49 sram0: memory@20000000 { 50 compatible = "mmio-sram"; 51 }; 52 53 sram1: memory@21000000 { 54 compatible = "zephyr,memory-region", "mmio-sram"; 55 zephyr,memory-region = "SRAM1"; 56 }; 57 58 clock: clock@41005000 { 59 compatible = "nordic,nrf-clock"; 60 reg = <0x41005000 0x1000>; 61 interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; 62 status = "okay"; 63 }; 64 65 power: power@41005000 { 66 compatible = "nordic,nrf-power"; 67 reg = <0x41005000 0x1000>; 68 interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; 69 status = "okay"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 73 gpregret1: gpregret1@4100551c { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "nordic,nrf-gpregret"; 77 reg = <0x4100551c 0x1>; 78 status = "okay"; 79 }; 80 81 gpregret2: gpregret2@41005520 { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 compatible = "nordic,nrf-gpregret"; 85 reg = <0x41005520 0x1>; 86 status = "okay"; 87 }; 88 }; 89 90 radio: radio@41008000 { 91 compatible = "nordic,nrf-radio"; 92 reg = <0x41008000 0x1000>; 93 interrupts = <8 NRF_DEFAULT_IRQ_PRIORITY>; 94 status = "okay"; 95 dfe-supported; 96 ieee802154-supported; 97 ble-2mbps-supported; 98 ble-coded-phy-supported; 99 100 ieee802154: ieee802154 { 101 compatible = "nordic,nrf-ieee802154"; 102 status = "disabled"; 103 }; 104 105 /* Note: In the nRF Connect SDK the SoftDevice Controller 106 * is added and set as the default Bluetooth Controller. 107 */ 108 bt_hci_controller: bt_hci_controller { 109 compatible = "zephyr,bt-hci-ll-sw-split"; 110 status = "okay"; 111 }; 112 }; 113 114 rng: random@41009000 { 115 compatible = "nordic,nrf-rng"; 116 reg = <0x41009000 0x1000>; 117 interrupts = <9 NRF_DEFAULT_IRQ_PRIORITY>; 118 status = "okay"; 119 }; 120 121 gpiote: gpiote0: gpiote@4100a000 { 122 compatible = "nordic,nrf-gpiote"; 123 reg = <0x4100a000 0x1000>; 124 interrupts = <10 5>; 125 status = "disabled"; 126 instance = <0>; 127 }; 128 129 wdt: wdt0: watchdog@4100b000 { 130 compatible = "nordic,nrf-wdt"; 131 reg = <0x4100b000 0x1000>; 132 interrupts = <11 NRF_DEFAULT_IRQ_PRIORITY>; 133 status = "okay"; 134 }; 135 136 timer0: timer@4100c000 { 137 compatible = "nordic,nrf-timer"; 138 status = "disabled"; 139 reg = <0x4100c000 0x1000>; 140 cc-num = <8>; 141 max-bit-width = <32>; 142 interrupts = <12 NRF_DEFAULT_IRQ_PRIORITY>; 143 prescaler = <0>; 144 }; 145 146 ecb: ecb@4100d000 { 147 compatible = "nordic,nrf-ecb"; 148 reg = <0x4100d000 0x1000>; 149 interrupts = <13 NRF_DEFAULT_IRQ_PRIORITY>; 150 status = "okay"; 151 }; 152 153 ccm: ccm@4100e000 { 154 compatible = "nordic,nrf-ccm"; 155 reg = <0x4100e000 0x1000>; 156 interrupts = <14 NRF_DEFAULT_IRQ_PRIORITY>; 157 length-field-length-8-bits; 158 headermask-supported; 159 status = "okay"; 160 }; 161 162 dppic0: dppic: dppic@4100f000 { 163 compatible = "nordic,nrf-dppic"; 164 reg = <0x4100f000 0x1000>; 165 status = "okay"; 166 }; 167 168 temp: temp@41010000 { 169 compatible = "nordic,nrf-temp"; 170 reg = <0x41010000 0x1000>; 171 interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>; 172 status = "okay"; 173 }; 174 175 rtc0: rtc@41011000 { 176 compatible = "nordic,nrf-rtc"; 177 reg = <0x41011000 0x1000>; 178 cc-num = <4>; 179 interrupts = <17 NRF_DEFAULT_IRQ_PRIORITY>; 180 status = "disabled"; 181 }; 182 183 mbox: ipc: mbox@41012000 { 184 compatible = "nordic,mbox-nrf-ipc", "nordic,nrf-ipc"; 185 reg = <0x41012000 0x1000>; 186 tx-mask = <0x0000ffff>; 187 rx-mask = <0x0000ffff>; 188 interrupts = <18 NRF_DEFAULT_IRQ_PRIORITY>; 189 #mbox-cells = <1>; 190 status = "okay"; 191 }; 192 193 i2c0: i2c@41013000 { 194 /* 195 * This i2c node can be TWIM or TWIS, 196 * for the user to pick: 197 * compatible = "nordic,nrf-twim" or 198 * "nordic,nrf-twis". 199 */ 200 compatible = "nordic,nrf-twim"; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 reg = <0x41013000 0x1000>; 204 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 205 easydma-maxcnt-bits = <16>; 206 status = "disabled"; 207 zephyr,pm-device-runtime-auto; 208 }; 209 210 spi0: spi@41013000 { 211 /* 212 * This spi node can be SPIM or SPIS, 213 * for the user to pick: 214 * compatible = "nordic,nrf-spim" or 215 * "nordic,nrf-spis". 216 */ 217 compatible = "nordic,nrf-spim"; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 reg = <0x41013000 0x1000>; 221 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 222 max-frequency = <DT_FREQ_M(8)>; 223 easydma-maxcnt-bits = <16>; 224 status = "disabled"; 225 }; 226 227 uart0: uart@41013000 { 228 compatible = "nordic,nrf-uarte"; 229 reg = <0x41013000 0x1000>; 230 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 231 status = "disabled"; 232 }; 233 234 egu0: egu@41014000 { 235 compatible = "nordic,nrf-egu"; 236 reg = <0x41014000 0x1000>; 237 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 238 status = "okay"; 239 }; 240 241 rtc1: rtc@41016000 { 242 compatible = "nordic,nrf-rtc"; 243 reg = <0x41016000 0x1000>; 244 cc-num = <4>; 245 interrupts = <22 NRF_DEFAULT_IRQ_PRIORITY>; 246 status = "disabled"; 247 }; 248 249 timer1: timer@41018000 { 250 compatible = "nordic,nrf-timer"; 251 status = "disabled"; 252 reg = <0x41018000 0x1000>; 253 cc-num = <8>; 254 max-bit-width = <32>; 255 interrupts = <24 NRF_DEFAULT_IRQ_PRIORITY>; 256 prescaler = <0>; 257 }; 258 259 timer2: timer@41019000 { 260 compatible = "nordic,nrf-timer"; 261 status = "disabled"; 262 reg = <0x41019000 0x1000>; 263 cc-num = <8>; 264 max-bit-width = <32>; 265 interrupts = <25 NRF_DEFAULT_IRQ_PRIORITY>; 266 prescaler = <0>; 267 }; 268 269 swi0: swi@4101a000 { 270 compatible = "nordic,nrf-swi"; 271 reg = <0x4101a000 0x1000>; 272 interrupts = <26 NRF_DEFAULT_IRQ_PRIORITY>; 273 status = "okay"; 274 }; 275 276 swi1: swi@4101b000 { 277 compatible = "nordic,nrf-swi"; 278 reg = <0x4101b000 0x1000>; 279 interrupts = <27 NRF_DEFAULT_IRQ_PRIORITY>; 280 status = "okay"; 281 }; 282 283 swi2: swi@4101c000 { 284 compatible = "nordic,nrf-swi"; 285 reg = <0x4101c000 0x1000>; 286 interrupts = <28 NRF_DEFAULT_IRQ_PRIORITY>; 287 status = "okay"; 288 }; 289 290 swi3: swi@4101d000 { 291 compatible = "nordic,nrf-swi"; 292 reg = <0x4101d000 0x1000>; 293 interrupts = <29 NRF_DEFAULT_IRQ_PRIORITY>; 294 status = "okay"; 295 }; 296 297 acl: acl@41080000 { 298 compatible = "nordic,nrf-acl"; 299 reg = <0x41080000 0x1000>; 300 status = "okay"; 301 }; 302 303 flash_controller: flash-controller@41080000 { 304 compatible = "nordic,nrf53-flash-controller"; 305 reg = <0x41080000 0x1000>; 306 partial-erase; 307 308 #address-cells = <1>; 309 #size-cells = <1>; 310 311 312 flash1: flash@1000000 { 313 compatible = "soc-nv-flash"; 314 erase-block-size = <2048>; 315 write-block-size = <4>; 316 }; 317 }; 318 319 vmc: vmc@41081000 { 320 compatible = "nordic,nrf-vmc"; 321 reg = <0x41081000 0x1000>; 322 status = "okay"; 323 }; 324 325 gpio0: gpio@418c0500 { 326 compatible = "nordic,nrf-gpio"; 327 gpio-controller; 328 reg = <0x418c0500 0x300>; 329 #gpio-cells = <2>; 330 status = "disabled"; 331 port = <0>; 332 gpiote-instance = <&gpiote>; 333 }; 334 335 gpio1: gpio@418c0800 { 336 compatible = "nordic,nrf-gpio"; 337 gpio-controller; 338 reg = <0x418c0800 0x300>; 339 #gpio-cells = <2>; 340 ngpios = <16>; 341 status = "disabled"; 342 port = <1>; 343 gpiote-instance = <&gpiote>; 344 }; 345 }; 346 347 /* Default IPC description */ 348 ipc { 349 ipc0: ipc0 { 350 compatible = "zephyr,ipc-icbmsg"; 351 status = "okay"; 352 mboxes = <&mbox 0>, <&mbox 1>; 353 mbox-names = "rx", "tx"; 354 tx-region = <&cpunet_cpuapp_ipc_shm>; 355 rx-region = <&cpuapp_cpunet_ipc_shm>; 356 tx-blocks = <32>; 357 rx-blocks = <32>; 358 }; 359 }; 360}; 361 362&nvic { 363 arm,num-irq-priority-bits = <3>; 364}; 365 366&systick { 367 /* Use RTC for system clock, instead of SysTick. */ 368 status = "disabled"; 369}; 370