Lines Matching +full:0 +full:x1000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
28 reg = <0x10000000 0x1000>;
35 reg = <0x10001000 0x1000>;
45 reg = <0x40000000 0x1000>;
46 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
55 reg = <0x4000051c 0x1>;
62 reg = <0x40000000 0x1000>;
63 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
69 reg = <0x40000000 0x1000>;
75 reg = <0x40001000 0x1000>;
87 reg = <0x40002000 0x1000>;
95 #size-cells = <0>;
96 reg = <0x40003000 0x1000>;
106 #size-cells = <0>;
107 reg = <0x40003000 0x1000>;
122 #size-cells = <0>;
123 reg = <0x40004000 0x1000>;
133 #size-cells = <0>;
134 reg = <0x40004000 0x1000>;
142 reg = <0x40006000 0x1000>;
145 instance = <0>;
150 reg = <0x40007000 0x1000>;
159 reg = <0x40008000 0x1000>;
163 prescaler = <0>;
169 reg = <0x40009000 0x1000>;
173 prescaler = <0>;
179 reg = <0x4000a000 0x1000>;
183 prescaler = <0>;
188 reg = <0x4000b000 0x1000>;
198 reg = <0x4000c000 0x1000>;
205 reg = <0x4000d000 0x1000>;
212 reg = <0x4000e000 0x1000>;
219 reg = <0x4000f000 0x1000>;
226 reg = <0x40010000 0x1000>;
233 reg = <0x40011000 0x1000>;
243 reg = <0x40012000 0x1000>;
250 reg = <0x40013000 0x1000>;
258 reg = <0x40014000 0x1000>;
265 reg = <0x40015000 0x1000>;
272 reg = <0x40016000 0x1000>;
279 reg = <0x40017000 0x1000>;
286 reg = <0x40018000 0x1000>;
293 reg = <0x40019000 0x1000>;
300 reg = <0x4001e000 0x1000>;
306 flash0: flash@0 {
315 reg = <0x4001f000 0x1000>;
322 reg = <0x50000000 0x1000>;
325 port = <0>;