Lines Matching +full:0 +full:x1000
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
44 reg = <0x4000d000 0x1000>;
50 reg = <0x40047000 0x2000>;
57 #clock-cells = <0>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
84 reg = <0x40064000 0x1000>;
90 reg = <0x40065000 0x4>;
96 reg = <0x40020000 0x1000>;
97 interrupts = <18 0>, <19 0>;
107 reg = <0x4003b000 0x1000>;
108 clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
109 <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
110 interrupts = <39 0>;
111 dmas = <&edma0 0 40>;
113 clk-source = <0>;
121 reg = <0x400ff000 0x40>;
131 reg = <0x400ff040 0x40>;
141 reg = <0x400ff080 0x40>;
151 reg = <0x400ff0c0 0x40>;
161 reg = <0x400ff100 0x40>;
172 #size-cells = <0>;
173 reg = <0x40066000 0x1000>;
174 interrupts = <24 0>;
175 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
183 #size-cells = <0>;
184 reg = <0x40067000 0x1000>;
185 interrupts = <25 0>;
186 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
194 #size-cells = <0>;
195 reg = <0x400e6000 0x1000>;
196 interrupts = <74 0>;
197 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
205 #size-cells = <0>;
206 reg = <0x400e7000 0x1000>;
207 interrupts = <91 0>;
208 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 7>;
214 reg = <0x400c4000 0x1000>;
215 interrupts = <30 0>;
216 clocks = <&sim KINETIS_SIM_BUS_CLK 0x102c 4>;
224 reg = <0x400c5000 0x1000>;
225 interrupts = <31 0>;
226 clocks = <&sim KINETIS_SIM_BUS_CLK 0x102c 5>;
234 reg = <0x400c6000 0x1000>;
235 interrupts = <32 0>;
236 clocks = <&sim KINETIS_SIM_BUS_CLK 0x102c 6>;
244 reg = <0x400c7000 0x1000>;
245 interrupts = <33 0>;
246 clocks = <&sim KINETIS_SIM_BUS_CLK 0x102c 7>;
254 reg = <0x400d6000 0x1000>;
255 interrupts = <34 0>;
256 clocks = <&sim KINETIS_SIM_BUS_CLK 0x102c 22>;
264 reg = <0x40049000 0x1000>;
265 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
270 reg = <0x4004a000 0x1000>;
271 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
276 reg = <0x4004b000 0x1000>;
277 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
282 reg = <0x4004c000 0x1000>;
283 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
288 reg = <0x4004d000 0x1000>;
289 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
294 reg = <0x40038000 0x1000>;
295 interrupts = <42 0>;
303 reg = <0x40039000 0x1000>;
304 interrupts = <43 0>;
312 reg = <0x4003a000 0x1000>;
313 interrupts = <44 0>;
321 reg = <0x400b9000 0x1000>;
322 interrupts = <71 0>;
330 reg = <0x4003d000 0x1000>;
331 interrupts = <46 0>, <47 0>;
339 reg = <0x4002c000 0x1000>;
341 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 12>;
343 #size-cells = <0>;
349 reg = <0x4002d000 0x1000>;
351 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 13>;
353 #size-cells = <0>;
359 reg = <0x400ac000 0x1000>;
361 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
363 #size-cells = <0>;
369 reg = <0x400a0000 0x1000>;
370 interrupts = <23 0>;
375 reg = <0x40072000 0x1000>;
384 reg = <0x40052000 0x1000>;
385 interrupts = <22 0>;
386 clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
391 reg = <0x40037000 0x1000>;
392 clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
394 max-load-value = <0xffffffff>;
396 #size-cells = <0>;
398 pit0_channel0: pit0_channel@0 {
400 reg = <0>;
401 interrupts = <48 0>;
408 interrupts = <49 0>;
415 interrupts = <50 0>;
422 interrupts = <51 0>;
434 reg = <0x40008000 0x1000>,
435 <0x40021000 0x1000>;
436 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
437 <4 0>, <5 0>, <6 0>, <7 0>,
438 <8 0>, <9 0>, <10 0>, <11 0>,
439 <12 0>, <13 0>, <14 0>, <15 0>,
440 <16 0>;
441 clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
442 <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;