1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-m33f";
20			reg = <0>;
21			#address-cells = <1>;
22			#size-cells = <1>;
23		};
24	};
25
26	/* Dummy pinctrl node, filled with pin mux options at board level */
27	pinctrl: pinctrl {
28		compatible = "nxp,port-pinctrl";
29		status = "okay";
30	};
31
32	soc {
33		syscon: syscon@40000000 {
34			compatible = "nxp,lpc-syscon";
35			reg = <0x40000000 0x4000>;
36			#clock-cells = <1>;
37			reset: reset {
38				compatible = "nxp,lpc-syscon-reset";
39				#reset-cells = <1>;
40			};
41		};
42
43		sramx: memory@4000000 {
44			compatible = "mmio-sram";
45			reg = <0x4000000 DT_SIZE_K(8)>;
46		};
47
48		sram0: memory@20000000 {
49			compatible = "mmio-sram";
50			reg = <0x20000000 DT_SIZE_K(120)>;
51		};
52
53		porta: pinmux@400bc000 {
54			compatible = "nxp,port-pinmux";
55			reg = <0x400bc000 0x1000>;
56			clocks = <&syscon MCUX_PORT0_CLK>;
57		};
58
59		portb: pinmux@400bd000 {
60			compatible = "nxp,port-pinmux";
61			reg = <0x400bd000 0x1000>;
62			clocks = <&syscon MCUX_PORT1_CLK>;
63		};
64
65		portc: pinmux@400be000 {
66			compatible = "nxp,port-pinmux";
67			reg = <0x400be000 0x1000>;
68			clocks = <&syscon MCUX_PORT2_CLK>;
69		};
70
71		portd: pinmux@400bf000 {
72			compatible = "nxp,port-pinmux";
73			reg = <0x400bf000 0x1000>;
74			clocks = <&syscon MCUX_PORT3_CLK>;
75		};
76
77		porte: pinmux@400c0000 {
78			compatible = "nxp,port-pinmux";
79			reg = <0x400c0000 0x1000>;
80			clocks = <&syscon MCUX_PORT4_CLK>;
81		};
82
83		gpio0: gpio@40102000 {
84			compatible = "nxp,kinetis-gpio";
85			reg = <0x40102000 0x1000>;
86			interrupts = <71 0>;
87			gpio-controller;
88			#gpio-cells = <2>;
89			nxp,kinetis-port = <&porta>;
90		};
91
92		gpio1: gpio@40103000 {
93			compatible = "nxp,kinetis-gpio";
94			status = "disabled";
95			reg = <0x40103000 0x1000>;
96			interrupts = <72 0>;
97			gpio-controller;
98			#gpio-cells = <2>;
99			nxp,kinetis-port = <&portb>;
100		};
101
102		gpio2: gpio@40104000 {
103			compatible = "nxp,kinetis-gpio";
104			status = "disabled";
105			reg = <0x40104000 0x1000>;
106			interrupts = <73 0>;
107			gpio-controller;
108			#gpio-cells = <2>;
109			nxp,kinetis-port = <&portc>;
110		};
111
112		gpio3: gpio@40105000 {
113			compatible = "nxp,kinetis-gpio";
114			status = "disabled";
115			reg = <0x40105000 0x1000>;
116			interrupts = <74 0>;
117			gpio-controller;
118			#gpio-cells = <2>;
119			nxp,kinetis-port = <&portd>;
120		};
121
122		gpio4: gpio@40106000 {
123			compatible = "nxp,kinetis-gpio";
124			status = "disabled";
125			reg = <0x40106000 0x1000>;
126			interrupts = <75 0>;
127			gpio-controller;
128			#gpio-cells = <2>;
129			nxp,kinetis-port = <&porte>;
130		};
131
132		lpuart0: lpuart@4009f000 {
133			compatible = "nxp,lpuart";
134			reg = <0x4009f000 0x1000>;
135			interrupts = <31 0>;
136			clocks = <&syscon MCUX_LPUART0_CLK>;
137		};
138
139		fmu: flash-controller@40095000 {
140			compatible = "nxp,msf1";
141			reg = <0x40095000 0x1000>;
142			interrupts = <12 0>;
143
144			#address-cells = <1>;
145			#size-cells = <1>;
146
147			flash: flash@0 {
148				compatible = "soc-nv-flash";
149				reg = <0 DT_SIZE_M(1)>;
150				erase-block-size = <8192>;
151				write-block-size = <128>;
152			};
153		};
154
155		ctimer0: ctimer@40004000 {
156			compatible = "nxp,lpc-ctimer";
157			reg = <0x40004000 0x1000>;
158			interrupts = <39 0>;
159			status = "disabled";
160			clk-source = <1>;
161			clocks = <&syscon MCUX_CTIMER0_CLK>;
162			mode = <0>;
163			input = <0>;
164			prescale = <0>;
165		};
166
167		ctimer1: ctimer@40005000 {
168			compatible = "nxp,lpc-ctimer";
169			reg = <0x40005000 0x1000>;
170			interrupts = <40 0>;
171			status = "disabled";
172			clk-source = <1>;
173			clocks = <&syscon MCUX_CTIMER1_CLK>;
174			mode = <0>;
175			input = <0>;
176			prescale = <0>;
177		};
178
179		ctimer2: ctimer@40006000 {
180			compatible = "nxp,lpc-ctimer";
181			reg = <0x40006000 0x1000>;
182			interrupts = <41 0>;
183			status = "disabled";
184			clk-source = <1>;
185			clocks = <&syscon MCUX_CTIMER2_CLK>;
186			mode = <0>;
187			input = <0>;
188			prescale = <0>;
189		};
190
191		ctimer3: ctimer@40007000 {
192			compatible = "nxp,lpc-ctimer";
193			reg = <0x40007000 0x1000>;
194			interrupts = <42 0>;
195			status = "disabled";
196			clk-source = <1>;
197			clocks = <&syscon MCUX_CTIMER3_CLK>;
198			mode = <0>;
199			input = <0>;
200			prescale = <0>;
201		};
202
203		ctimer4: ctimer@40008000 {
204			compatible = "nxp,lpc-ctimer";
205			reg = <0x40008000 0x1000>;
206			interrupts = <43 0>;
207			status = "disabled";
208			clk-source = <1>;
209			clocks = <&syscon MCUX_CTIMER4_CLK>;
210			mode = <0>;
211			input = <0>;
212			prescale = <0>;
213		};
214
215		dac0: dac@400b4000 {
216			compatible = "nxp,lpdac";
217			reg = <0x400b4000 0x1000>;
218			interrupts = <67 0>;
219			status = "disabled";
220			voltage-reference = <0>;
221			#io-channel-cells = <1>;
222		};
223
224		flexpwm0: flexpwm@400a9000 {
225			compatible = "nxp,flexpwm";
226			reg = <0x400a9000 0x1000>;
227			interrupt-names = "RELOAD-ERROR", "FAULT";
228			interrupts = <44 0>, <45 0>;
229			flexpwm0_pwm0: pwm0 {
230				compatible = "nxp,imx-pwm";
231				index = <0>;
232				interrupts = <46 0>;
233				#pwm-cells = <3>;
234				clocks = <&syscon MCUX_BUS_CLK>;
235				nxp,prescaler = <128>;
236				status = "disabled";
237				run-in-wait;
238			};
239
240			flexpwm0_pwm1: pwm1 {
241				compatible = "nxp,imx-pwm";
242				index = <1>;
243				interrupts = <47 0>;
244				#pwm-cells = <3>;
245				clocks = <&syscon MCUX_BUS_CLK>;
246				nxp,prescaler = <128>;
247				status = "disabled";
248				run-in-wait;
249			};
250
251			flexpwm0_pwm2: pwm2 {
252				compatible = "nxp,imx-pwm";
253				index = <2>;
254				interrupts = <48 0>;
255				#pwm-cells = <3>;
256				clocks = <&syscon MCUX_BUS_CLK>;
257				nxp,prescaler = <128>;
258				status = "disabled";
259				run-in-wait;
260			};
261		};
262
263		flexpwm1: flexpwm@d0000 {
264			compatible = "nxp,flexpwm";
265			reg = <0xd0000 0x1000>;
266			interrupt-names = "RELOAD-ERROR", "FAULT";
267			interrupts = <79 0>, <80 0>;
268			flexpwm1_pwm0: pwm0 {
269				compatible = "nxp,imx-pwm";
270				index = <0>;
271				interrupts = <81 0>;
272				#pwm-cells = <3>;
273				clocks = <&syscon MCUX_BUS_CLK>;
274				nxp,prescaler = <128>;
275				status = "disabled";
276				run-in-wait;
277			};
278
279			flexpwm1_pwm1: pwm1 {
280				compatible = "nxp,imx-pwm";
281				index = <1>;
282				interrupts = <82 0>;
283				#pwm-cells = <3>;
284				clocks = <&syscon MCUX_BUS_CLK>;
285				nxp,prescaler = <128>;
286				status = "disabled";
287				run-in-wait;
288			};
289
290			flexpwm1_pwm2: pwm2 {
291				compatible = "nxp,imx-pwm";
292				index = <2>;
293				interrupts = <83 0>;
294				#pwm-cells = <3>;
295				clocks = <&syscon MCUX_BUS_CLK>;
296				nxp,prescaler = <128>;
297				status = "disabled";
298				run-in-wait;
299			};
300		};
301
302		lpadc0: lpadc@400af000 {
303			compatible = "nxp,lpc-lpadc";
304			reg = <0x400af000 0x1000>;
305			interrupts = <62 0>;
306			status = "disabled";
307			clk-divider = <1>;
308			clk-source = <0>;
309			voltage-ref= <2>;
310			calibration-average = <128>;
311			power-level = <0>;
312			offset-value-a = <0>;
313			offset-value-b = <0>;
314			#io-channel-cells = <1>;
315			clocks = <&syscon MCUX_LPADC1_CLK>;
316		};
317
318		lpadc1: lpadc@400b0000 {
319			compatible = "nxp,lpc-lpadc";
320			reg = <0x400b0000 0x1000>;
321			interrupts = <63 0>;
322			status = "disabled";
323			clk-divider = <1>;
324			clk-source = <0>;
325			voltage-ref= <2>;
326			calibration-average = <128>;
327			power-level = <1>;
328			offset-value-a = <0>;
329			offset-value-b = <0>;
330			#io-channel-cells = <1>;
331			clocks = <&syscon MCUX_LPADC2_CLK>;
332		};
333
334		lpcmp0: lpcmp@400b1000 {
335			compatible = "nxp,lpcmp";
336			reg = <0x400b1000 0x1000>;
337			interrupts = <64 0>;
338			status = "disabled";
339			#io-channel-cells = <2>;
340		};
341
342		lpcmp1: lpcmp@400b2000 {
343			compatible = "nxp,lpcmp";
344			reg = <0x400b2000 0x1000>;
345			interrupts = <65 0>;
346			status = "disabled";
347			#io-channel-cells = <2>;
348		};
349
350		lpi2c0: i2c@4009a000 {
351			compatible = "nxp,lpi2c";
352			clock-frequency = <I2C_BITRATE_STANDARD>;
353			#address-cells = <1>;
354			#size-cells = <0>;
355			reg = <0x4009a000 0x1000>;
356			interrupts = <26 0>;
357			clocks = <&syscon MCUX_LPI2C0_CLK>;
358			status = "disabled";
359		};
360
361		lpi2c1: i2c@4009b000 {
362			compatible = "nxp,lpi2c";
363			clock-frequency = <I2C_BITRATE_STANDARD>;
364			#address-cells = <1>;
365			#size-cells = <0>;
366			reg = <0x4009b000 0x1000>;
367			interrupts = <27 0>;
368			clocks = <&syscon MCUX_LPI2C1_CLK>;
369			status = "disabled";
370		};
371
372		lpi2c2: i2c@400d4000 {
373			compatible = "nxp,lpi2c";
374			clock-frequency = <I2C_BITRATE_STANDARD>;
375			#address-cells = <1>;
376			#size-cells = <0>;
377			reg = <0x400d4000 0x1000>;
378			interrupts = <77 0>;
379			clocks = <&syscon MCUX_LPI2C2_CLK>;
380			status = "disabled";
381		};
382
383		lpi2c3: i2c@400d5000 {
384			compatible = "nxp,lpi2c";
385			clock-frequency = <I2C_BITRATE_STANDARD>;
386			#address-cells = <1>;
387			#size-cells = <0>;
388			reg = <0x400d5000 0x1000>;
389			interrupts = <78 0>;
390			clocks = <&syscon MCUX_LPI2C3_CLK>;
391			status = "disabled";
392		};
393
394		lptmr0: lptmr@400ab000 {
395			compatible = "nxp,lptmr";
396			reg = <0x400ab000 0x1000>;
397			interrupts = <55 0>;
398			clock-frequency = <16000>;
399			prescaler = <1>;
400			clk-source = <1>;
401			resolution = <32>;
402			status = "disabled";
403		};
404
405		usb: usbd@400a4000 {
406			compatible = "nxp,kinetis-usbd";
407			reg = <0x400a4000 0x1000>;
408			interrupts = <36 1>;
409			interrupt-names = "usb";
410			num-bidir-endpoints = <16>;
411			status = "disabled";
412			no-voltage-regulator;
413		};
414	};
415};
416
417&nvic {
418	arm,num-irq-priority-bits = <3>;
419};
420