Lines Matching +full:0 +full:x1000
16 #size-cells = <0>;
18 cpu0: cpu@0 {
20 reg = <0>;
35 reg = <0x40000000 0x4000>;
45 reg = <0x4000000 DT_SIZE_K(8)>;
50 reg = <0x20000000 DT_SIZE_K(120)>;
55 reg = <0x400bc000 0x1000>;
61 reg = <0x400bd000 0x1000>;
67 reg = <0x400be000 0x1000>;
73 reg = <0x400bf000 0x1000>;
79 reg = <0x400c0000 0x1000>;
85 reg = <0x40102000 0x1000>;
86 interrupts = <71 0>;
95 reg = <0x40103000 0x1000>;
96 interrupts = <72 0>;
105 reg = <0x40104000 0x1000>;
106 interrupts = <73 0>;
115 reg = <0x40105000 0x1000>;
116 interrupts = <74 0>;
125 reg = <0x40106000 0x1000>;
126 interrupts = <75 0>;
134 reg = <0x4009f000 0x1000>;
135 interrupts = <31 0>;
141 reg = <0x40095000 0x1000>;
142 interrupts = <12 0>;
147 flash: flash@0 {
149 reg = <0 DT_SIZE_M(1)>;
157 reg = <0x40004000 0x1000>;
158 interrupts = <39 0>;
162 mode = <0>;
163 input = <0>;
164 prescale = <0>;
169 reg = <0x40005000 0x1000>;
170 interrupts = <40 0>;
174 mode = <0>;
175 input = <0>;
176 prescale = <0>;
181 reg = <0x40006000 0x1000>;
182 interrupts = <41 0>;
186 mode = <0>;
187 input = <0>;
188 prescale = <0>;
193 reg = <0x40007000 0x1000>;
194 interrupts = <42 0>;
198 mode = <0>;
199 input = <0>;
200 prescale = <0>;
205 reg = <0x40008000 0x1000>;
206 interrupts = <43 0>;
210 mode = <0>;
211 input = <0>;
212 prescale = <0>;
217 reg = <0x400b4000 0x1000>;
218 interrupts = <67 0>;
220 voltage-reference = <0>;
226 reg = <0x400a9000 0x1000>;
228 interrupts = <44 0>, <45 0>;
231 index = <0>;
232 interrupts = <46 0>;
243 interrupts = <47 0>;
254 interrupts = <48 0>;
265 reg = <0xd0000 0x1000>;
267 interrupts = <79 0>, <80 0>;
270 index = <0>;
271 interrupts = <81 0>;
282 interrupts = <82 0>;
293 interrupts = <83 0>;
304 reg = <0x400af000 0x1000>;
305 interrupts = <62 0>;
308 clk-source = <0>;
311 power-level = <0>;
312 offset-value-a = <0>;
313 offset-value-b = <0>;
320 reg = <0x400b0000 0x1000>;
321 interrupts = <63 0>;
324 clk-source = <0>;
328 offset-value-a = <0>;
329 offset-value-b = <0>;
336 reg = <0x400b1000 0x1000>;
337 interrupts = <64 0>;
344 reg = <0x400b2000 0x1000>;
345 interrupts = <65 0>;
354 #size-cells = <0>;
355 reg = <0x4009a000 0x1000>;
356 interrupts = <26 0>;
365 #size-cells = <0>;
366 reg = <0x4009b000 0x1000>;
367 interrupts = <27 0>;
376 #size-cells = <0>;
377 reg = <0x400d4000 0x1000>;
378 interrupts = <77 0>;
387 #size-cells = <0>;
388 reg = <0x400d5000 0x1000>;
389 interrupts = <78 0>;
396 reg = <0x400ab000 0x1000>;
397 interrupts = <55 0>;
407 reg = <0x400a4000 0x1000>;