Lines Matching +full:0 +full:x1000
17 #size-cells = <0>;
19 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
49 reg = <0x4000000 DT_SIZE_K(96)>;
64 reg = <0x20000000 DT_SIZE_K(416)>;
72 syscon: syscon@0 {
74 reg = <0x0 0x4000>;
84 reg = <0x116000 0x1000>;
90 reg = <0x117000 0x1000>;
96 reg = <0x118000 0x1000>;
102 reg = <0x119000 0x1000>;
108 reg = <0x11a000 0x1000>;
114 reg = <0x42000 0x1000>;
121 reg = <0x96000 0x1000>;
122 interrupts = <17 0>,<18 0>;
131 reg = <0x98000 0x1000>;
132 interrupts = <19 0>,<20 0>;
141 reg = <0x9a000 0x1000>;
142 interrupts = <21 0>,<22 0>;
151 reg = <0x9c000 0x1000>;
152 interrupts = <23 0>,<24 0>;
161 reg = <0x9e000 0x1000>;
162 interrupts = <25 0>,<26 0>;
171 reg = <0x40000 0x1000>;
172 interrupts = <27 0>,<28 0>;
180 reg = <0x92000 0x1000>;
181 interrupts = <35 0>;
191 reg = <0x92000 0x1000>;
197 reg = <0x92000 0x1000>;
200 #size-cells = <0>;
205 reg = <0x92800 0x1000>;
208 #size-cells = <0>;
215 reg = <0x93000 0x1000>;
216 interrupts = <36 0>;
225 reg = <0x93000 0x1000>;
227 /* DMA channels 0 and 1, muxed to LPUART1 RX and TX */
228 dmas = <&edma0 0 71>, <&edma0 1 72>;
234 reg = <0x93000 0x1000>;
237 #size-cells = <0>;
238 /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
239 dmas = <&edma0 0 71>, <&edma0 1 72>;
245 reg = <0x93800 0x1000>;
248 #size-cells = <0>;
255 reg = <0x94000 0x1000>;
256 interrupts = <37 0>;
265 reg = <0x94000 0x1000>;
274 reg = <0x94000 0x1000>;
277 #size-cells = <0>;
285 reg = <0x94800 0x1000>;
288 #size-cells = <0>;
295 reg = <0x95000 0x1000>;
296 interrupts = <38 0>;
305 reg = <0x95000 0x1000>;
311 reg = <0x95000 0x1000>;
314 #size-cells = <0>;
319 reg = <0x95800 0x1000>;
322 #size-cells = <0>;
329 reg = <0xb4000 0x1000>;
330 interrupts = <39 0>;
339 reg = <0xb4000 0x1000>;
348 reg = <0xb4000 0x1000>;
351 #size-cells = <0>;
359 reg = <0xb4800 0x1000>;
362 #size-cells = <0>;
369 reg = <0xb5000 0x1000>;
370 interrupts = <40 0>;
379 reg = <0xb5000 0x1000>;
385 reg = <0xb5000 0x1000>;
388 #size-cells = <0>;
393 reg = <0xb5800 0x1000>;
396 #size-cells = <0>;
403 reg = <0xb6000 0x1000>;
404 interrupts = <41 0>;
413 reg = <0xb6000 0x1000>;
419 reg = <0xb6000 0x1000>;
422 #size-cells = <0>;
427 reg = <0xb6800 0x1000>;
430 #size-cells = <0>;
437 reg = <0xb7000 0x1000>;
438 interrupts = <42 0>;
447 reg = <0xb7000 0x1000>;
453 reg = <0xb7000 0x1000>;
456 #size-cells = <0>;
461 reg = <0xb7800 0x1000>;
464 #size-cells = <0>;
471 reg = <0xb8000 0x1000>;
472 interrupts = <43 0>;
481 reg = <0xb8000 0x1000>;
487 reg = <0xb8000 0x1000>;
490 #size-cells = <0>;
495 reg = <0xb8800 0x1000>;
498 #size-cells = <0>;
505 reg = <0xb9000 0x1000>;
506 interrupts = <44 0>;
515 reg = <0xb9000 0x1000>;
521 reg = <0xb9000 0x1000>;
524 #size-cells = <0>;
529 reg = <0xb9800 0x1000>;
532 #size-cells = <0>;
544 reg = <0x80000 0x1000>;
545 interrupts = <1 0>, <2 0>, <3 0>, <4 0>,
546 <5 0>, <6 0>, <7 0>, <8 0>,
547 <9 0>, <10 0>, <11 0>, <12 0>,
548 <13 0>, <14 0>, <15 0>, <16 0>;
560 reg = <0xa0000 0x1000>;
561 interrupts = <77 0>, <78 0>, <79 0>, <80 0>,
562 <81 0>, <82 0>, <83 0>, <84 0>,
563 <85 0>, <86 0>, <87 0>, <88 0>,
564 <89 0>, <90 0>, <91 0>, <92 0>;
571 reg = <0x43000 0x1000>;
572 interrupts = <138 0>;
578 flash: flash@0 {
580 reg = <0 DT_SIZE_M(2)>;
588 reg = <0x1100000 0x10>;
594 reg = <0x49000 0x1000>;
595 interrupts = <57 0>;
601 reg = < 0x10f000 0x1000>;
602 interrupts = <106 0>;
604 voltage-reference = <0>;
610 reg = < 0x112000 0x1000>;
611 interrupts = <107 0>;
613 voltage-reference = <0>;
619 reg = <0x40100000 0x1200>;
624 interrupts = <139 0>, <140 0>, <141 0>;
629 #size-cells = <0>;
637 reg = <0x16000 0x1000>;
638 interrupts = <152 0>;
645 reg = <0xce000 0x1000>;
647 interrupts = <112 0>, <113 0>;
650 index = <0>;
651 interrupts = <114 0>;
662 interrupts = <115 0>;
673 interrupts = <116 0>;
684 interrupts = <117 0>;
695 reg = <0xd0000 0x1000>;
697 interrupts = <118 0>, <119 0>;
700 index = <0>;
701 interrupts = <120 0>;
712 interrupts = <121 0>;
723 interrupts = <122 0>;
734 interrupts = <123 0>;
745 reg = <0xc000 0x1000>;
746 interrupts = <31 0>;
750 mode = <0>;
751 input = <0>;
752 prescale = <0>;
757 reg = <0xd000 0x1000>;
758 interrupts = <32 0>;
762 mode = <0>;
763 input = <0>;
764 prescale = <0>;
769 reg = <0xe000 0x1000>;
770 interrupts = <34 0>;
774 mode = <0>;
775 input = <0>;
776 prescale = <0>;
781 reg = <0xf000 0x1000>;
782 interrupts = <55 0>;
786 mode = <0>;
787 input = <0>;
788 prescale = <0>;
793 reg = <0x10000 0x1000>;
794 interrupts = <56 0>;
798 mode = <0>;
799 input = <0>;
800 prescale = <0>;
805 reg = <0x91000 0x1000>;
806 interrupts = <33 0>;
815 reg = <0x33000 0x1000>;
817 interrupts = <53 0>;
818 program-mem = <0x4000000>;
819 #dma-cells = <0>;
824 reg = <0x109000 0x1000>;
825 interrupts = <61 0>;
835 reg = <0x111000 0x14>;
847 reg = <0x10d000 0x1000>;
848 interrupts = <45 0>;
852 power-level = <0>;
853 offset-value-a = <0>;
854 offset-value-b = <0>;
862 reg = <0x10e000 0x1000>;
863 interrupts = <46 0>;
865 voltage-ref= <0>;
868 offset-value-a = <0>;
869 offset-value-b = <0>;
876 reg = <0x10b000 0x1000>;
877 interrupts = <67 0>;
885 reg = <0x10a000 0x1000>;
891 reg = <0x51000 0x1000>;
892 interrupts = <109 0>;
899 reg = <0x52000 0x1000>;
900 interrupts = <110 0>;
907 reg = <0x53000 0x1000>;
908 interrupts = <111 0>;
915 reg = <0xd4000 0x4000>;
916 interrupts = <62 0>;
919 clk-source = <0>;
925 reg = <0xd8000 0x4000>;
926 interrupts = <63 0>;
929 clk-source = <0>;
935 reg = <0x4a000 0x1000>;
936 interrupts = <143 0>;
945 reg = <0x4b000 0x1000>;
946 interrupts = <144 0>;
955 reg = <0x21000 0x1000>;
956 interrupts = <95 0>;
963 #size-cells = <0>;
968 reg = <0x22000 0x1000>;
969 interrupts = <96 0>;
976 #size-cells = <0>;
981 reg = <0x105000 0x1000>;
983 interrupts = <105 0>;
993 reg = <0x13000 0x1000>;
994 interrupts = <30 0>;
998 resets = <&reset NXP_SYSCON_RESET(1, 0)>;
1000 #size-cells = <0>;
1002 mrt0_channel0: mrt0_channel@0 {
1004 reg = <0>;
1026 reg = <0x4c000 0x1000>;
1028 interrupts = <52 0>;
1031 clock-src = <0>;
1046 interrupts = <58 0>;
1048 #size-cells = <0>;