Lines Matching +full:0 +full:x1000
21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0xe0000000 0x1000>;
41 reg = <0x10000000 0x1000>;
48 reg = <0x10001000 0x1000>;
58 reg = <0x40000000 0x1000>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
65 reg = <0x40000000 0x1000>;
66 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
75 reg = <0x4000051c 0x1>;
83 reg = <0x40000520 0x1>;
89 reg = <0x40000578 0x1>;
96 reg = <0x40000580 0x1>;
104 reg = <0x40001000 0x1000>;
131 reg = <0x40002000 0x1000>;
146 #size-cells = <0>;
147 reg = <0x40003000 0x1000>;
164 #size-cells = <0>;
165 reg = <0x40003000 0x1000>;
182 #size-cells = <0>;
183 reg = <0x40004000 0x1000>;
200 #size-cells = <0>;
201 reg = <0x40004000 0x1000>;
210 reg = <0x40006000 0x1000>;
213 instance = <0>;
219 reg = <0x40008000 0x1000>;
223 prescaler = <0>;
229 reg = <0x40009000 0x1000>;
233 prescaler = <0>;
239 reg = <0x4000a000 0x1000>;
243 prescaler = <0>;
248 reg = <0x4000b000 0x1000>;
258 reg = <0x4000c000 0x1000>;
265 reg = <0x4000d000 0x1000>;
272 reg = <0x4000e000 0x1000>;
279 reg = <0x4000f000 0x1000>;
288 reg = <0x40010000 0x1000>;
295 reg = <0x40011000 0x1000>;
305 reg = <0x40012000 0x1000>;
312 reg = <0x40013000 0x1000>;
319 reg = <0x40014000 0x1000>;
326 reg = <0x40015000 0x1000>;
333 reg = <0x40016000 0x1000>;
340 reg = <0x40017000 0x1000>;
347 reg = <0x40018000 0x1000>;
354 reg = <0x40019000 0x1000>;
362 reg = <0x4001a000 0x1000>;
366 prescaler = <0>;
371 reg = <0x4001e000 0x1000>;
377 reg = <0x4001e000 0x1000>;
384 flash0: flash@0 {
393 reg = <0x4001f000 0x1000>;
399 reg = <0x40027000 0x1000>;
412 reg = <0x50000000 0x200
413 0x50000500 0x300>;
416 port = <0>;