Lines Matching +full:0 +full:x1000
21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
33 reg = <0x10000000 0x1000>;
40 reg = <0x10001000 0x1000>;
50 reg = <0x40000000 0x1000>;
51 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
57 reg = <0x40000000 0x1000>;
58 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>;
67 reg = <0x4000051c 0x1>;
75 reg = <0x40000520 0x1>;
81 reg = <0x40000578 0x1>;
89 reg = <0x40000000 0x1000>;
95 reg = <0x40001000 0x1000>;
113 reg = <0x40002000 0x1000>;
128 #size-cells = <0>;
129 reg = <0x40003000 0x1000>;
146 #size-cells = <0>;
147 reg = <0x40004000 0x1000>;
156 reg = <0x40006000 0x1000>;
159 instance = <0>;
164 reg = <0x40007000 0x1000>;
173 reg = <0x40008000 0x1000>;
177 prescaler = <0>;
183 reg = <0x40009000 0x1000>;
187 prescaler = <0>;
193 reg = <0x4000a000 0x1000>;
197 prescaler = <0>;
202 reg = <0x4000b000 0x1000>;
212 reg = <0x4000c000 0x1000>;
219 reg = <0x4000d000 0x1000>;
226 reg = <0x4000e000 0x1000>;
233 reg = <0x4000f000 0x1000>;
241 reg = <0x40010000 0x1000>;
248 reg = <0x40011000 0x1000>;
258 reg = <0x40012000 0x1000>;
265 reg = <0x40014000 0x1000>;
272 reg = <0x40015000 0x1000>;
279 reg = <0x40016000 0x1000>;
286 reg = <0x40017000 0x1000>;
293 reg = <0x40018000 0x1000>;
300 reg = <0x40019000 0x1000>;
307 reg = <0x4001e000 0x1000>;
314 flash0: flash@0 {
323 reg = <0x4001f000 0x1000>;
330 reg = <0x50000000 0x1000>;
333 port = <0>;