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/Zephyr-latest/dts/bindings/clock/
Dnxp,imx-anatop.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: i.MX ANATOP (Analog Clock Controller Module) IP node
6 compatible: "nxp,imx-anatop"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 description: Number of items to expect in a clock specifier
20 "#pll-clock-cells":
24 description: Number of items to expect in a PLL specifier
26 clock-cells:
27 - name
[all …]
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
[all …]
Dst,stm32l0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32L0 and STM32L1 Main PLL node binding:
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
10 The desired PLL frequency can be computed with the following formula:
12 f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
14 with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16 The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
[all …]
Dst,stm32f1-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
8 as input clock.
10 Output clock frequency can be computed with the following formula:
12 f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)
14 The PLL output frequency must not exceed 72 MHz.
17 compatible: "st,stm32f1-pll-clock"
19 include: [clock-controller.yaml, base.yaml]
22 "#clock-cells":
32 Main PLL multiplication factor for VCO
[all …]
Dst,stm32g0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32G0 devices
7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 64 MHz.
[all …]
Dst,stm32f2-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F2 Main PLL node binding:
7 Takes one of clk_hse or clk_hsi as input clock.
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
17 The PLL output frequency must not exceed 168 MHz.
20 compatible: "st,stm32f2-pll-clock"
22 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32f4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F4 Main PLL node binding:
7 Takes one of clk_hse or clk_hsi as input clock, with an
8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
11 Up to 2 output clocks could be supported and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19 The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
[all …]
Dst,stm32wb-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB and STM32WL PLL node.
7 It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8 Only main PLL is supported for now.
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
[all …]
Dst,stm32f7-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F7 Main PLL node binding:
7 Takes one of clk_hse or clk_hsi as input clock.
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
[all …]
Dst,stm32u0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32U0 Main PLL node binding:
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 The PLL output frequency must not exceed 122 MHz.
[all …]
Dst,stm32f4-plli2s-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32F4 PLL I2S node binding:
7 Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
11 f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
13 with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
16 compatible: "st,stm32f4-plli2s-clock"
18 include: [clock-controller.yaml, base.yaml]
21 "#clock-cells":
24 mul-n:
29 Valid range may vary between parts: 50 - 432 , 192 - 432
[all …]
Dst,stm32l4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32L4 and STM32L5 devices
7 It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8 Only main PLL is supported for now.
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
[all …]
Dst,stm32h7-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PLL node binding for STM32H7 devices
7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
10 These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
18 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
19 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
21 with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
[all …]
Dst,stm32f105-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
7 Takes one of clk_hse, pll2 or clk_hsi as input clock.
8 When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
11 Output clock frequency can be computed with the following formula:
13 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
19 The PLL output frequency must not exceed 72 MHz.
22 compatible: "st,stm32f105-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
13 compatible = "mmio-sram";
17 flash-controller@407e0000 {
19 #address-cells = <1>;
20 #size-cells = <1>;
23 compatible = "soc-nv-flash";
29 compatible = "renesas,ra-sce7-rng";
34 channel-count = <11>;
[all …]
Dr7fa6e2bx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f100Xb.dtsi6 * SPDX-License-Identifier: Apache-2.0
18 /delete-node/ pll;
20 pll: pll { label
21 #clock-cells = <0>;
22 compatible = "st,stm32f100-pll-clock";
28 compatible = "st,stm32f100", "st,stm32f1", "simple-bus";
30 flash-controller@40022000 {
33 erase-block-size = <DT_SIZE_K(1)>;
38 compatible = "st,stm32-spi";
39 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/riscv/wch/
Dch32v00x.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "wch,qingke-v2";
25 clock-frequency = <DT_FREQ_M(48)>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
13 /delete-node/ &adc1;
18 compatible = "mmio-sram";
23 compatible = "renesas,ra-gpio-ioport";
26 gpio-controller;
27 #gpio-cells = <2>;
[all …]
Dr7fa4e2b93cfm.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 /delete-node/ &iic0;
[all …]
Dr7fa4w1ad2cng.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
20 flash-controller@407e0000 {
22 compatible = "soc-nv-flash";
28 compatible = "renesas,ra-sci";
30 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa4m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
24 gpio-controller;
25 #gpio-cells = <2>;
31 compatible = "renesas,ra-gpio-ioport";
[all …]

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