1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra8/ra8x1.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9
10/ {
11	clocks: clocks {
12		#address-cells = <1>;
13		#size-cells = <1>;
14
15		xtal: clock-main-osc {
16			compatible = "renesas,ra-cgc-external-clock";
17			clock-frequency = <DT_FREQ_M(20)>;
18			#clock-cells = <0>;
19			status = "disabled";
20		};
21
22		hoco: clock-hoco {
23			compatible = "fixed-clock";
24			clock-frequency = <DT_FREQ_M(48)>;
25			#clock-cells = <0>;
26		};
27
28		moco: clock-moco {
29			compatible = "fixed-clock";
30			clock-frequency = <DT_FREQ_M(8)>;
31			#clock-cells = <0>;
32		};
33
34		loco: clock-loco {
35			compatible = "fixed-clock";
36			clock-frequency = <32768>;
37			#clock-cells = <0>;
38		};
39
40		subclk: clock-subclk {
41			compatible = "renesas,ra-cgc-subclk";
42			clock-frequency = <32768>;
43			#clock-cells = <0>;
44			status = "disabled";
45		};
46
47		pll: pll {
48			compatible = "renesas,ra-cgc-pll";
49			#clock-cells = <0>;
50
51			/* PLL */
52			clocks = <&xtal>;
53			div = <2>;
54			mul = <96 0>;
55
56			pllp: pllp {
57				compatible = "renesas,ra-cgc-pll-out";
58				div = <2>;
59				freq = <DT_FREQ_M(480)>;
60				status = "disabled";
61				#clock-cells = <0>;
62			};
63
64			pllq: pllq {
65				compatible = "renesas,ra-cgc-pll-out";
66				div = <2>;
67				freq = <DT_FREQ_M(480)>;
68				status = "disabled";
69				#clock-cells = <0>;
70			};
71
72			pllr: pllr {
73				compatible = "renesas,ra-cgc-pll-out";
74				div = <2>;
75				freq = <DT_FREQ_M(480)>;
76				status = "disabled";
77				#clock-cells = <0>;
78			};
79			status = "disabled";
80		};
81
82		pll2: pll2 {
83			compatible = "renesas,ra-cgc-pll";
84			#clock-cells = <0>;
85
86			/* PLL2 */
87			div = <2>;
88			mul = <96 0>;
89
90			pll2p: pll2p {
91				compatible = "renesas,ra-cgc-pll-out";
92				div = <2>;
93				freq = <DT_FREQ_M(0)>;
94				status = "disabled";
95				#clock-cells = <0>;
96			};
97
98			pll2q: pll2q {
99				compatible = "renesas,ra-cgc-pll-out";
100				div = <2>;
101				freq = <DT_FREQ_M(0)>;
102				status = "disabled";
103				#clock-cells = <0>;
104			};
105
106			pll2r: pll2r {
107				compatible = "renesas,ra-cgc-pll-out";
108				div = <2>;
109				freq = <DT_FREQ_M(0)>;
110				status = "disabled";
111				#clock-cells = <0>;
112			};
113			status = "disabled";
114		};
115
116		pclkblock: pclkblock@40203000 {
117			compatible = "renesas,ra-cgc-pclk-block";
118			reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
119			      <0x4020300c 4>, <0x40203010 4>;
120			reg-names = "MSTPA", "MSTPB","MSTPC",
121				    "MSTPD", "MSTPE";
122			#clock-cells = <0>;
123			clocks = <&pllp>;
124			status = "okay";
125
126			cpuclk: cpuclk {
127				compatible = "renesas,ra-cgc-pclk";
128				div = <1>;
129				#clock-cells = <2>;
130				status = "okay";
131			};
132
133			iclk: iclk {
134				compatible = "renesas,ra-cgc-pclk";
135				div = <2>;
136				#clock-cells = <2>;
137				status = "okay";
138			};
139
140			pclka: pclka {
141				compatible = "renesas,ra-cgc-pclk";
142				div = <4>;
143				#clock-cells = <2>;
144				status = "okay";
145			};
146
147			pclkb: pclkb {
148				compatible = "renesas,ra-cgc-pclk";
149				div = <8>;
150				#clock-cells = <2>;
151				status = "okay";
152			};
153
154			pclkc: pclkc {
155				compatible = "renesas,ra-cgc-pclk";
156				div = <8>;
157				#clock-cells = <2>;
158				status = "okay";
159			};
160
161			pclkd: pclkd {
162				compatible = "renesas,ra-cgc-pclk";
163				div = <4>;
164				#clock-cells = <2>;
165				status = "okay";
166			};
167
168			pclke: pclke {
169				compatible = "renesas,ra-cgc-pclk";
170				div = <2>;
171				#clock-cells = <2>;
172				status = "okay";
173			};
174
175			bclk: bclk {
176				compatible = "renesas,ra-cgc-pclk";
177				div = <4>;
178				bclkout: bclkout {
179					compatible = "renesas,ra-cgc-busclk";
180					clk-out-div = <2>;
181					sdclk = <1>;
182					#clock-cells = <0>;
183				};
184				#clock-cells = <2>;
185				status = "okay";
186			};
187
188			fclk: fclk {
189				compatible = "renesas,ra-cgc-pclk";
190				div = <8>;
191				#clock-cells = <2>;
192				status = "okay";
193			};
194
195			clkout: clkout {
196				compatible = "renesas,ra-cgc-pclk";
197				#clock-cells = <2>;
198				status = "disabled";
199			};
200
201			sciclk: sciclk {
202				compatible = "renesas,ra-cgc-pclk";
203				#clock-cells = <2>;
204				status = "disabled";
205			};
206
207			spiclk: spiclk {
208				compatible = "renesas,ra-cgc-pclk";
209				#clock-cells = <2>;
210				status = "disabled";
211			};
212
213			canfdclk: canfdclk {
214				compatible = "renesas,ra-cgc-pclk";
215				#clock-cells = <2>;
216				status = "disabled";
217			};
218
219			i3cclk: i3cclk {
220				compatible = "renesas,ra-cgc-pclk";
221				#clock-cells = <2>;
222				status = "disabled";
223			};
224
225			uclk: uclk {
226				compatible = "renesas,ra-cgc-pclk";
227				#clock-cells = <2>;
228				status = "disabled";
229			};
230
231			u60clk: u60clk {
232				compatible = "renesas,ra-cgc-pclk";
233				#clock-cells = <2>;
234				status = "disabled";
235			};
236
237			octaspiclk: octaspiclk {
238				compatible = "renesas,ra-cgc-pclk";
239				#clock-cells = <2>;
240				status = "disabled";
241			};
242		};
243	};
244
245	soc {
246		usbhs: usbhs@40351000 {
247			compatible = "renesas,ra-usb";
248			reg = <0x40351000 0x2000>;
249			interrupts = <54 12>, <55 12>, <56 12>;
250			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
251			num-bidir-endpoints = <10>;
252			phys = <&usbhs_phy>;
253			status = "disabled";
254			udc {
255				compatible = "renesas,ra-udc";
256				status = "disabled";
257			};
258		};
259	};
260
261	usbhs_phy: usbhs-phy {
262		compatible = "renesas,ra-usbphyc";
263		#phy-cells = <0>;
264	};
265};
266
267&ioport0 {
268	port-irqs = <&port_irq6 &port_irq7 &port_irq8
269	&port_irq9 &port_irq10 &port_irq11
270	&port_irq12 &port_irq13 &port_irq14>;
271	port-irq-names = "port-irq6",
272			 "port-irq7",
273			 "port-irq8",
274			 "port-irq9",
275			 "port-irq10",
276			 "port-irq11",
277			 "port-irq12",
278			 "port-irq13",
279			 "port-irq14";
280	port-irq6-pins = <0>;
281	port-irq7-pins = <1>;
282	port-irq8-pins = <2>;
283	port-irq9-pins = <4>;
284	port-irq10-pins = <5>;
285	port-irq11-pins = <6>;
286	port-irq12-pins = <8>;
287	port-irq13-pins = <9 15>;
288	port-irq14-pins = <10>;
289};
290
291&ioport1 {
292	port-irqs = <&port_irq0 &port_irq1 &port_irq2>;
293	port-irq-names = "port-irq0",
294			 "port-irq1",
295			 "port-irq2";
296	port-irq0-pins = <5>;
297	port-irq1-pins = <1 4>;
298	port-irq2-pins = <0>;
299};
300
301&ioport2 {
302	port-irqs = <&port_irq0 &port_irq1 &port_irq2
303	&port_irq3>;
304	port-irq-names = "port-irq0",
305			 "port-irq1",
306			 "port-irq2",
307			 "port-irq3";
308	port-irq0-pins = <6>;
309	port-irq1-pins = <5>;
310	port-irq2-pins = <3 13>;
311	port-irq3-pins = <2 8 12>;
312};
313
314&ioport3 {
315	port-irqs = <&port_irq4 &port_irq5 &port_irq6
316	&port_irq8 &port_irq9>;
317	port-irq-names = "port-irq4",
318			 "port-irq5",
319			 "port-irq6",
320			 "port-irq8",
321			 "port-irq9";
322	port-irq4-pins = <0>;
323	port-irq5-pins = <2>;
324	port-irq6-pins = <1>;
325	port-irq8-pins = <5>;
326	port-irq9-pins = <4>;
327};
328
329&ioport4 {
330	port-irqs = <&port_irq0 &port_irq4 &port_irq5
331	&port_irq6 &port_irq7 &port_irq8
332	&port_irq9 &port_irq14 &port_irq15>;
333	port-irq-names = "port-irq0",
334			 "port-irq4",
335			 "port-irq5",
336			 "port-irq6",
337			 "port-irq7",
338			 "port-irq8",
339			 "port-irq9",
340			 "port-irq14",
341			 "port-irq15";
342	port-irq0-pins = <0>;
343	port-irq4-pins = <2 11>;
344	port-irq5-pins = <1 10>;
345	port-irq6-pins = <9>;
346	port-irq7-pins = <8>;
347	port-irq8-pins = <15>;
348	port-irq9-pins = <14>;
349	port-irq14-pins = <3>;
350	port-irq15-pins = <4>;
351};
352
353&ioport5 {
354	port-irqs = <&port_irq1 &port_irq2 &port_irq3
355	&port_irq14 &port_irq15>;
356	port-irq-names = "port-irq1",
357			 "port-irq2",
358			 "port-irq3",
359			 "port-irq14",
360			 "port-irq15";
361	port-irq1-pins = <8>;
362	port-irq2-pins = <9>;
363	port-irq3-pins = <10>;
364	port-irq14-pins = <12>;
365	port-irq15-pins = <11>;
366};
367
368&ioport6 {
369	port-irqs = <&port_irq7>;
370	port-irq-names = "port-irq7";
371	port-irq7-pins = <15>;
372};
373
374&ioport7 {
375	port-irqs = <&port_irq7 &port_irq8 &port_irq10
376	&port_irq11>;
377	port-irq-names = "port-irq7",
378			 "port-irq8",
379			 "port-irq10",
380			 "port-irq11";
381	port-irq7-pins = <6>;
382	port-irq8-pins = <7>;
383	port-irq10-pins = <9>;
384	port-irq11-pins = <8>;
385};
386
387&ioport8 {
388	port-irqs = <&port_irq0 &port_irq11 &port_irq12
389	&port_irq14 &port_irq15>;
390	port-irq-names = "port-irq0",
391			 "port-irq11",
392			 "port-irq12",
393			 "port-irq14",
394			 "port-irq15";
395	port-irq0-pins = <6>;
396	port-irq11-pins = <0>;
397	port-irq12-pins = <1>;
398	port-irq14-pins = <4>;
399	port-irq15-pins = <8>;
400};
401
402&ioport9 {
403	port-irqs = <&port_irq8 &port_irq9 &port_irq10
404	&port_irq11>;
405	port-irq-names = "port-irq8",
406			 "port-irq9",
407			 "port-irq10",
408			 "port-irq11";
409	port-irq8-pins = <5>;
410	port-irq9-pins = <6>;
411	port-irq10-pins = <7>;
412	port-irq11-pins = <8>;
413};
414
415&ioporta {
416	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
417	port-irq-names = "port-irq4",
418			 "port-irq5",
419			 "port-irq6";
420	port-irq4-pins = <10>;
421	port-irq5-pins = <9>;
422	port-irq6-pins = <8>;
423};
424