1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32F4 Main PLL node binding:
6
7  Takes one of clk_hse or clk_hsi as input clock, with an
8  input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
9  in this acceptable range.
10
11  Up to 2 output clocks could be supported and for each output clock, the
12  frequency can be computed with the following formula:
13
14    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
15    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
16
17      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18
19  The PLL output frequency must not exceed 80 MHz.
20
21
22compatible: "st,stm32f4-pll-clock"
23
24include: [clock-controller.yaml, base.yaml]
25
26properties:
27  "#clock-cells":
28    const: 0
29
30  clocks:
31    required: true
32
33  div-m:
34    type: int
35    required: true
36    description: |
37        Division factor for the PLL input clock
38        Valid range: 2 - 63
39
40  mul-n:
41    type: int
42    required: true
43    description: |
44        Main PLL multiplication factor for VCO
45        Valid range: 50 - 432
46
47  div-p:
48    type: int
49    required: true
50    description: |
51        Main PLL division factor for PLLSAI2CLK
52    enum:
53      - 2
54      - 4
55      - 6
56      - 8
57
58  div-q:
59    type: int
60    description: |
61        Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
62        generator clocks.
63        Valid range: 2 - 15
64
65  div-r:
66    type: int
67    description: |
68        Main PLL (PLL) division factor for I2S and DFSDM
69        generator clocks.
70        Valid range: 2 - 7
71