Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
8   as input clock.
10   Output clock frequency can be computed with the following formula:
12     f(PLLCLK) = f(input clk) x PLLMUL  --> SYSCLK (System Clock)
14   The PLL output frequency must not exceed 72 MHz.
17 compatible: "st,stm32f1-pll-clock"
19 include: [clock-controller.yaml, base.yaml]
22   "#clock-cells":
32         Main PLL multiplication factor for VCO
33         Valid range: 2 - 16
38         Optional HSE divider for PLL entry
43         Optional PLL output divisor to generate a 48MHz USB clock.
44         When set, PLL clock is not divided.
45         Otherwise, PLL output clock is divided by 1.5.