1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
6
7  Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
8  as input clock.
9
10  Output clock frequency can be computed with the following formula:
11
12    f(PLLCLK) = f(input clk) x PLLMUL  --> SYSCLK (System Clock)
13
14  The PLL output frequency must not exceed 72 MHz.
15
16
17compatible: "st,stm32f1-pll-clock"
18
19include: [clock-controller.yaml, base.yaml]
20
21properties:
22  "#clock-cells":
23    const: 0
24
25  clocks:
26    required: true
27
28  mul:
29    type: int
30    required: true
31    description: |
32        Main PLL multiplication factor for VCO
33        Valid range: 2 - 16
34
35  xtpre:
36    type: boolean
37    description: |
38        Optional HSE divider for PLL entry
39
40  usbpre:
41    type: boolean
42    description: |
43        Optional PLL output divisor to generate a 48MHz USB clock.
44        When set, PLL clock is not divided.
45        Otherwise, PLL output clock is divided by 1.5.
46