1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/ra_clock.h>
8#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
9
10/delete-node/ &agt0;
11/delete-node/ &agt1;
12/delete-node/ &agt2;
13/delete-node/ &agt3;
14/delete-node/ &agt4;
15/delete-node/ &agt5;
16/delete-node/ &iic0;
17/delete-node/ &iic1;
18
19/delete-node/ &adc1;
20
21/ {
22	soc {
23		sram0: memory@20000000 {
24			compatible = "mmio-sram";
25			reg = <0x20000000 DT_SIZE_K(40)>;
26		};
27
28		ioport8: gpio@40080100 {
29			compatible = "renesas,ra-gpio-ioport";
30			reg = <0x40080100 0x20>;
31			port = <8>;
32			gpio-controller;
33			#gpio-cells = <2>;
34			ngpios = <16>;
35			status = "disabled";
36		};
37
38		flash-controller@407e0000 {
39			reg = <0x407e0000 0x10000>;
40			#address-cells = <1>;
41			#size-cells = <1>;
42			flash0: flash@0 {
43				compatible = "soc-nv-flash";
44				reg = <0x0 DT_SIZE_K(128)>;
45			};
46		};
47
48		adc@40170000 {
49			channel-count = <12>;
50			channel-available-mask = <0x139f7>;
51		};
52
53		id_code: id_code@100a120 {
54			compatible = "zephyr,memory-region";
55			reg = <0x0100a120 0x10>;
56			zephyr,memory-region = "ID_CODE";
57			status = "okay";
58		};
59
60		canfd_global: canfd_global@400b0000 {
61			compatible = "renesas,ra-canfd-global";
62			interrupts = <40 1>, <41 1>;
63			interrupt-names = "rxf", "glerr";
64			clocks = <&pclkb 0 0>, <&pclka 0 0>;
65			clock-names = "opclk", "ramclk";
66			reg = <0x400b0000 0x2000>;
67			status = "disabled";
68
69			canfd0: canfd0 {
70				compatible = "renesas,ra-canfd";
71				channel = <0>;
72				interrupts = <43 12>, <44 12>, <45 12>;
73				interrupt-names = "err", "tx", "rx";
74				clocks = <&canfdclk MSTPC 27>;
75				clock-names = "dllclk";
76				status = "disabled";
77			};
78		};
79
80		trng: trng {
81			compatible = "renesas,ra-trng";
82			status = "disabled";
83		};
84	};
85
86	clocks: clocks {
87		#address-cells = <1>;
88		#size-cells = <1>;
89
90		xtal: clock-main-osc {
91			compatible = "renesas,ra-cgc-external-clock";
92			clock-frequency = <DT_FREQ_M(20)>;
93			#clock-cells = <0>;
94			status = "disabled";
95		};
96
97		hoco: clock-hoco {
98			compatible = "fixed-clock";
99			clock-frequency = <DT_FREQ_M(20)>;
100			#clock-cells = <0>;
101		};
102
103		moco: clock-moco {
104			compatible = "fixed-clock";
105			clock-frequency = <DT_FREQ_M(8)>;
106			#clock-cells = <0>;
107		};
108
109		loco: clock-loco {
110			compatible = "fixed-clock";
111			clock-frequency = <32768>;
112			#clock-cells = <0>;
113		};
114
115		subclk: clock-subclk {
116			compatible = "renesas,ra-cgc-subclk";
117			clock-frequency = <32768>;
118			#clock-cells = <0>;
119			status = "disabled";
120		};
121
122		pll: pll {
123			compatible = "renesas,ra-cgc-pll";
124			#clock-cells = <0>;
125
126			/* PLL */
127			clocks = <&xtal>;
128			div = <1>;
129			mul = <10 0>;
130			status = "disabled";
131		};
132
133		pclkblock: pclkblock@40084000 {
134			compatible = "renesas,ra-cgc-pclk-block";
135			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
136			      <0x4008400c 4>, <0x40084010 4>;
137			reg-names = "MSTPA", "MSTPB","MSTPC",
138				    "MSTPD", "MSTPE";
139			#clock-cells = <0>;
140			clocks = <&pll>;
141			status = "okay";
142
143			iclk: iclk {
144				compatible = "renesas,ra-cgc-pclk";
145				div = <2>;
146				#clock-cells = <2>;
147				status = "okay";
148			};
149
150			pclka: pclka {
151				compatible = "renesas,ra-cgc-pclk";
152				div = <2>;
153				#clock-cells = <2>;
154				status = "okay";
155			};
156
157			pclkb: pclkb {
158				compatible = "renesas,ra-cgc-pclk";
159				div = <4>;
160				#clock-cells = <2>;
161				status = "okay";
162			};
163
164			pclkc: pclkc {
165				compatible = "renesas,ra-cgc-pclk";
166				div = <4>;
167				#clock-cells = <2>;
168				status = "okay";
169			};
170
171			pclkd: pclkd {
172				compatible = "renesas,ra-cgc-pclk";
173				div = <2>;
174				#clock-cells = <2>;
175				status = "okay";
176			};
177
178			fclk: fclk {
179				compatible = "renesas,ra-cgc-pclk";
180				div = <4>;
181				#clock-cells = <2>;
182				status = "okay";
183			};
184
185			clkout: clkout {
186				compatible = "renesas,ra-cgc-pclk";
187				#clock-cells = <2>;
188				status = "disabled";
189			};
190
191			uclk: uclk {
192				compatible = "renesas,ra-cgc-pclk";
193				#clock-cells = <2>;
194				status = "disabled";
195			};
196
197			canfdclk: canfdclk {
198				compatible = "renesas,ra-cgc-pclk";
199				#clock-cells = <2>;
200				status = "disabled";
201			};
202
203			i3cclk: i3cclk {
204				compatible = "renesas,ra-cgc-pclk";
205				#clock-cells = <2>;
206				status = "disabled";
207			};
208
209			cecclk: cecclk {
210				compatible = "renesas,ra-cgc-pclk";
211				#clock-cells = <2>;
212				status = "disabled";
213			};
214		};
215	};
216};
217
218&ioport0 {
219	port-irqs = <&port_irq6 &port_irq7 &port_irq8
220	&port_irq9 &port_irq10 &port_irq11
221	&port_irq12 &port_irq13>;
222	port-irq-names = "port-irq6",
223			 "port-irq7",
224			 "port-irq8",
225			 "port-irq9",
226			 "port-irq10",
227			 "port-irq11",
228			 "port-irq12",
229			 "port-irq13";
230	port-irq6-pins = <0>;
231	port-irq7-pins = <1>;
232	port-irq8-pins = <2>;
233	port-irq9-pins = <4>;
234	port-irq10-pins = <5>;
235	port-irq11-pins = <6>;
236	port-irq12-pins = <8>;
237	port-irq13-pins = <15>;
238};
239
240&ioport1 {
241	port-irqs = <&port_irq0 &port_irq1 &port_irq2
242	&port_irq3 &port_irq4>;
243	port-irq-names = "port-irq0",
244			 "port-irq1",
245			 "port-irq2",
246			 "port-irq3",
247			 "port-irq4";
248	port-irq0-pins = <5>;
249	port-irq1-pins = <1 4>;
250	port-irq2-pins = <0>;
251	port-irq3-pins = <10>;
252	port-irq4-pins = <11>;
253};
254
255&ioport2 {
256	port-irqs = <&port_irq0 &port_irq1 &port_irq2
257	&port_irq3>;
258	port-irq-names = "port-irq0",
259			 "port-irq1",
260			 "port-irq2",
261			 "port-irq3";
262	port-irq0-pins = <6>;
263	port-irq1-pins = <5>;
264	port-irq2-pins = <13>;
265	port-irq3-pins = <12>;
266};
267
268&ioport3 {
269	port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
270	port-irq-names = "port-irq5",
271			 "port-irq6",
272			 "port-irq9";
273	port-irq5-pins = <2>;
274	port-irq6-pins = <1>;
275	port-irq9-pins = <4>;
276};
277
278&ioport4 {
279	port-irqs = <&port_irq0 &port_irq4 &port_irq5
280	&port_irq6 &port_irq7 &port_irq14>;
281	port-irq-names = "port-irq0",
282			 "port-irq4",
283			 "port-irq5",
284			 "port-irq6",
285			 "port-irq7",
286			 "port-irq14";
287	port-irq0-pins = <0>;
288	port-irq4-pins = <2 11>;
289	port-irq5-pins = <1 10>;
290	port-irq6-pins = <9>;
291	port-irq7-pins = <8>;
292	port-irq14-pins = <3>;
293};
294
295&ioport8 {
296	port-irqs = <&port_irq11>;
297	port-irq-names = "port-irq11";
298	port-irq11-pins = <14>;
299};
300