/*
 * Copyright (c) 2024 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>

/delete-node/ &agt0;
/delete-node/ &agt1;
/delete-node/ &agt2;
/delete-node/ &agt3;
/delete-node/ &agt4;
/delete-node/ &agt5;
/delete-node/ &iic0;
/delete-node/ &iic1;

/delete-node/ &adc1;

/ {
	soc {
		sram0: memory@20000000 {
			compatible = "mmio-sram";
			reg = <0x20000000 DT_SIZE_K(40)>;
		};

		ioport8: gpio@40080100 {
			compatible = "renesas,ra-gpio-ioport";
			reg = <0x40080100 0x20>;
			port = <8>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <16>;
			status = "disabled";
		};

		flash-controller@407e0000 {
			reg = <0x407e0000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;
			flash0: flash@0 {
				compatible = "soc-nv-flash";
				reg = <0x0 DT_SIZE_K(128)>;
			};
		};

		adc@40170000 {
			channel-count = <12>;
			channel-available-mask = <0x139f7>;
		};

		id_code: id_code@100a120 {
			compatible = "zephyr,memory-region";
			reg = <0x0100a120 0x10>;
			zephyr,memory-region = "ID_CODE";
			status = "okay";
		};

		canfd_global: canfd_global@400b0000 {
			compatible = "renesas,ra-canfd-global";
			interrupts = <40 1>, <41 1>;
			interrupt-names = "rxf", "glerr";
			clocks = <&pclkb 0 0>, <&pclka 0 0>;
			clock-names = "opclk", "ramclk";
			reg = <0x400b0000 0x2000>;
			status = "disabled";

			canfd0: canfd0 {
				compatible = "renesas,ra-canfd";
				channel = <0>;
				interrupts = <43 12>, <44 12>, <45 12>;
				interrupt-names = "err", "tx", "rx";
				clocks = <&canfdclk MSTPC 27>;
				clock-names = "dllclk";
				status = "disabled";
			};
		};

		trng: trng {
			compatible = "renesas,ra-trng";
			status = "disabled";
		};
	};

	clocks: clocks {
		#address-cells = <1>;
		#size-cells = <1>;

		xtal: clock-main-osc {
			compatible = "renesas,ra-cgc-external-clock";
			clock-frequency = <DT_FREQ_M(20)>;
			#clock-cells = <0>;
			status = "disabled";
		};

		hoco: clock-hoco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(20)>;
			#clock-cells = <0>;
		};

		moco: clock-moco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(8)>;
			#clock-cells = <0>;
		};

		loco: clock-loco {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};

		subclk: clock-subclk {
			compatible = "renesas,ra-cgc-subclk";
			clock-frequency = <32768>;
			#clock-cells = <0>;
			status = "disabled";
		};

		pll: pll {
			compatible = "renesas,ra-cgc-pll";
			#clock-cells = <0>;

			/* PLL */
			clocks = <&xtal>;
			div = <1>;
			mul = <10 0>;
			status = "disabled";
		};

		pclkblock: pclkblock@40084000 {
			compatible = "renesas,ra-cgc-pclk-block";
			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
			      <0x4008400c 4>, <0x40084010 4>;
			reg-names = "MSTPA", "MSTPB","MSTPC",
				    "MSTPD", "MSTPE";
			#clock-cells = <0>;
			clocks = <&pll>;
			status = "okay";

			iclk: iclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclka: pclka {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkb: pclkb {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkc: pclkc {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkd: pclkd {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			fclk: fclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			clkout: clkout {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			uclk: uclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			canfdclk: canfdclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			i3cclk: i3cclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			cecclk: cecclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};
		};
	};
};

&ioport0 {
	port-irqs = <&port_irq6 &port_irq7 &port_irq8
	&port_irq9 &port_irq10 &port_irq11
	&port_irq12 &port_irq13>;
	port-irq-names = "port-irq6",
			 "port-irq7",
			 "port-irq8",
			 "port-irq9",
			 "port-irq10",
			 "port-irq11",
			 "port-irq12",
			 "port-irq13";
	port-irq6-pins = <0>;
	port-irq7-pins = <1>;
	port-irq8-pins = <2>;
	port-irq9-pins = <4>;
	port-irq10-pins = <5>;
	port-irq11-pins = <6>;
	port-irq12-pins = <8>;
	port-irq13-pins = <15>;
};

&ioport1 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2
	&port_irq3 &port_irq4>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2",
			 "port-irq3",
			 "port-irq4";
	port-irq0-pins = <5>;
	port-irq1-pins = <1 4>;
	port-irq2-pins = <0>;
	port-irq3-pins = <10>;
	port-irq4-pins = <11>;
};

&ioport2 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2
	&port_irq3>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2",
			 "port-irq3";
	port-irq0-pins = <6>;
	port-irq1-pins = <5>;
	port-irq2-pins = <13>;
	port-irq3-pins = <12>;
};

&ioport3 {
	port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
	port-irq-names = "port-irq5",
			 "port-irq6",
			 "port-irq9";
	port-irq5-pins = <2>;
	port-irq6-pins = <1>;
	port-irq9-pins = <4>;
};

&ioport4 {
	port-irqs = <&port_irq0 &port_irq4 &port_irq5
	&port_irq6 &port_irq7 &port_irq14>;
	port-irq-names = "port-irq0",
			 "port-irq4",
			 "port-irq5",
			 "port-irq6",
			 "port-irq7",
			 "port-irq14";
	port-irq0-pins = <0>;
	port-irq4-pins = <2 11>;
	port-irq5-pins = <1 10>;
	port-irq6-pins = <9>;
	port-irq7-pins = <8>;
	port-irq14-pins = <3>;
};

&ioport8 {
	port-irqs = <&port_irq11>;
	port-irq-names = "port-irq11";
	port-irq11-pins = <14>;
};