1# Copyright (c) 2024 STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32U0 Main PLL node binding:
6
7  Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
8  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
9  clock in this acceptable range.
10
11  PLL can have up to 3 output clocks and for each output clock, the
12  frequency can be computed with the following formulae:
13
14    f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
15    f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
17
18      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19
20  The PLL output frequency must not exceed 122 MHz.
21
22compatible: "st,stm32u0-pll-clock"
23
24include: [clock-controller.yaml, base.yaml]
25
26properties:
27  "#clock-cells":
28    const: 0
29
30  clocks:
31    required: true
32
33  div-m:
34    type: int
35    required: true
36    description: |
37        Division factor M of the PLL
38        input clock divider
39        Valid range: 1 - 8
40
41  mul-n:
42    type: int
43    required: true
44    description: |
45        PLL frequency multiplication factor N
46        Valid range: 4 - 127
47
48  div-p:
49    type: int
50    description: |
51        PLL VCO division factor P
52        Valid range: 2 - 32
53
54  div-q:
55    type: int
56    description: |
57        PLL VCO division factor Q
58        Valid range: 2 - 8
59
60  div-r:
61    type: int
62    required: true
63    description: |
64        PLL VCO division factor R
65        Valid range: 2 - 8
66