Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   PLL node binding for STM32H7 devices
7   It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
10   These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
12   clock in this acceptable range.
14   Each PLL can have up to 3 output clocks and for each output clock, the
17     f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
18     f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
19     f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
21       with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
23   The PLL output frequency must not exceed 80 MHz.
25 compatible: "st,stm32h7-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
30   "#clock-cells":
36   div-m:
41         input clock
42         Valid range: 1 - 63
44   mul-n:
48         Main PLL multiplication factor for VCOx
49         Valid range: 4 - 512
51   div-p:
54         PLL division factor for pllx_p_ck
55         Valid range: 1 - 128
57   div-q:
60         PLL division factor for pllx_q_ck
61         Valid range: 1 - 128
63   div-r:
66         PLL division factor for pllx_r_ck
67         Valid range: 1 - 128
73         Valid range: 0 - 8191