1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL node binding for STM32H7 devices
6
7  It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
8  Only PLL1 and PLL3 are supported for now.
9
10  These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
11  an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
12  clock in this acceptable range.
13
14  Each PLL can have up to 3 output clocks and for each output clock, the
15  frequency can be computed with the following formulae:
16
17    f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
18    f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
19    f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
20
21      with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
22
23  The PLL output frequency must not exceed 80 MHz.
24
25compatible: "st,stm32h7-pll-clock"
26
27include: [clock-controller.yaml, base.yaml]
28
29properties:
30  "#clock-cells":
31    const: 0
32
33  clocks:
34    required: true
35
36  div-m:
37    type: int
38    required: true
39    description: |
40        Division factor for PLLx
41        input clock
42        Valid range: 1 - 63
43
44  mul-n:
45    type: int
46    required: true
47    description: |
48        Main PLL multiplication factor for VCOx
49        Valid range: 4 - 512
50
51  div-p:
52    type: int
53    description: |
54        PLL division factor for pllx_p_ck
55        Valid range: 1 - 128
56
57  div-q:
58    type: int
59    description: |
60        PLL division factor for pllx_q_ck
61        Valid range: 1 - 128
62
63  div-r:
64    type: int
65    description: |
66        PLL division factor for pllx_r_ck
67        Valid range: 1 - 128
68
69  fracn:
70    type: int
71    description: |
72        PLLx FRACN value
73        Valid range: 0 - 8191
74