Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   STM32L0 and STM32L1 Main PLL node binding:
7   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
10   The desired PLL frequency can be computed with the following formula:
12     f(PLL) = f(VCO clock) / PLLDIV  --> PLLCLK (System Clock)
14       with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16   The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23   "#clock-cells":
33         PLL output division
35       - 2
36       - 3
37       - 4
43         PLL multiplication factor for VCO
44         The PLL VCO clock frequency must not exceed:
45         - 96 MHz when the product is in Range 1
46         - 48 MHz when the product is in Range 2
47         - 24 MHz when the product is in Range 3
48         If the USB uses the PLL as clock source, the PLL VCO clock must be
51       - 3
52       - 4
53       - 6
54       - 8
55       - 12
56       - 16
57       - 24
58       - 32
59       - 48