1# Copyright (c) 2021, Microchip Technology Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: Microchip XEC Power Clock Reset and VBAT register (PCR)
5
6compatible: "microchip,xec-pcr"
7
8include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
9
10properties:
11  reg:
12    required: true
13
14  core-clock-div:
15    type: int
16    required: true
17    description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
18
19  slow-clock-div:
20    type: int
21    description: |
22      PWM and TACH clock domain divided down from 48 MHz AHB clock. The
23      default value is 480 for 100 kHz.
24
25  pll-32k-src:
26    type: int
27    required: true
28    description: 32 KHz clock source for PLL
29
30  periph-32k-src:
31    type: int
32    required: true
33    description: 32 KHz clock source for peripherals
34
35  xtal-single-ended:
36    type: boolean
37    description: Use single ended crystal connection to XTAL2 pin.
38
39  clk32kmon-period-min:
40    type: int
41    required: true
42    description: |
43      32KHz clock monitor minimum valid 32KHz period in 48MHz units
44
45  clk32kmon-period-max:
46    type: int
47    required: true
48    description: |
49      32KHz clock monitor maximum valid 32KHz period in 48MHz units
50
51  clk32kmon-duty-cycle-var-max:
52    type: int
53    required: true
54    description: |
55      Maximum duty cycle variation. Difference in units of 48HMz between
56      the measured 32KHz high and low pulse widths.
57
58  clk32kmon-valid-min:
59    type: int
60    required: true
61    description: |
62      Minimum number of consecutive 32KHz pulses that pass all monitor tests
63
64  xtal-enable-delay-ms:
65    type: int
66    required: true
67    default: 300
68    description: |
69      Delay in milliseconds after crystal is enabled and clock monitor is
70      started.
71
72  pll-lock-timeout-ms:
73    type: int
74    required: true
75    default: 30
76    description: |
77      Timeout in milliseconds waiting for PLL to lock to new clock source.
78
79  clkmon-bypass:
80    type: boolean
81    description: Bypass clkmon check of crystal or XTAL2 single-ended clock.
82
83  internal-osc-disable:
84    type: boolean
85    description: |
86      If the internal silicon 32KHz oscillator is not chosen as the source
87      for PLL and Periheral devices then disable the internal 32KHz
88      oscillator to save power.
89
90  "#clock-cells":
91    const: 3
92
93clock-cells:
94  - regidx
95  - bitpos
96  - domain
97